LM9810CCWM National Semiconductor, LM9810CCWM Datasheet - Page 16

• Manufacturer Part Number: LM9810CCWM
• Description: LM9810/20 10/12-Bit Image Sensor Processor Analog Front End
• Manufacturer: National Semiconductor

example, the R offset and gain settings will be used for the first
conversion following a falling edge on
set to Single Input Color (001).
For the Single Input Color, Bayer and Green Stripe modes, the
mux will always connect the
and gain settings will alternate values every pixel according to the
order indicated by the Sampler and Color Mode register (see
Table 2). The first falling edge of
Sampler and Color Mode register will ready the offset and gain to
cycle through the colors of the first line of the programmed color
mode. Each subsequent falling edge of
set and gain settings to the first color of the next line. The
LM9810/20’s unused OS inputs should not be left unconnected.
All three OS inputs should be tied together on the LM9810/20
side of the clamp capacitor (see Figure 3).
For the Line Rate Color mode, the mux will cycle through the
OS
and B offset & gain settings will be used when the mux is set to
the
gain settings will always be used on the first line following a write
register 0.
1.5 Data Latency
The latency through the LM9810/20 is 8
one
b9 - b4) represents data whose reference signal was sampled 8
t
1.6 Programmable Gain
The output of the Sampler drives the input of the x3 Boost gain
stage. The gain of the x3 Boost gain is 3V/V if bit B5 of the cur-
rent color’s gain register (registers 4,5, and 6) is set, or 1V/V if bit
B5 is cleared. The output of the x3 gain stage is the input to the
offset DAC and the output of the offset DAC is the input to the
PGA (Programmable Gain Amplifier). The PGA provides 5 bits of
gain correction over a 0.93V/V to 3V/V (-0.6 to 9.5dB) range. The
x3 Boost gain stage and the PGA can be combined for an overall
gain range of .93V/V to 9.0V/V (-.6 to 19dB). The gain setting for
each color (registers 4, 5 and 6) should be set during calibration
to bring the maximum amplitude of the strongest pixel to a level
just below the desired maximum output from the ADC. The PGA
gain is determined by the following equation:
If the x3 Boost gain is enabled then the overall signal gain will be
three times the PGA gain.
SampCLK
G
OS
MCLK
and
Figure 3: OS Connections for single output sensors
PGA Gain
R
,
OS
OS
+ t
period. The data output on
G
B
MCLK
SENSOR
inputs after each falling edge of
and
OS
V
--- -
V
+ t
DOS
OS
Equation 1: PGA Gain
B
SampSU
=
input, respectively.
0.933 + .0667 (value in bits B4-B0)
C
NC
CLAMP
OS
earlier (see Diagram 1).
B
input to the sampler. The offset
NewLine
NewLine
D5
OS
OS
OS
NewLine
LM9810/20
-
G
B
R
OS
following a write to the
SampCLK
D0
R
if the color mode is
(MSBs b11 - b6 or
NewLine
and the R offset &
will switch the off-
periods plus
. The R, G
OS
R
,
16
1.7 Offset DAC
The Offset DAC removes the DC offsets generated by the sensor
and the LM9810/20’s analog signal chain (see section 1.7.1,
Internal Offsets). The DAC value for each color (registers 1,2 and
3) should be set during calibration to the lowest value that still
results in an ADC output code greater than zero for all the pixels
when scanning a black line. With a PGA gain of 1V/V, each LSB
of the offset DAC typically adds the equivalent of 5 LM9810 LSBs
or 20 LM9820 LSBs, providing a total offset adjustment range of
±150 LM9810 LSBs or ±590 LM9820 LSBs. The Offset DAC’s
output voltage is given by:
In terms of output codes, the offset is given by:
The offset is positive if bit B5 is cleared and negative if B5 is set.
Since the analog offset is added before the PGA gain, the value
of the PGA gain must be considered when selecting the offset
DAC values.
1.7.1 Internal Offsets
Figure 4 is a model of the LM9810/20’s internal offsets. Equation
5 shows how to calculate the expected output code given the
input voltage (V
V
grammed gains (G
stant C.
C is a constant that combines the gain error through the AFE, ref-
erence voltage variance, and analog voltage to digital code con-
version into one constant. Ideally, C = 2048 codes/V (4096
codes/2V) for the LM9820 and 512 codes/V (1024 codes/2V) for
the LM9810. Manufacturing tolerances widen the range of C (see
Electrical Specifications).
Equation 6 is a simplification of the output code calculation,
neglecting the LM9810/20’s internal offsets.
D
OS3
Equation 5: Output code calculation with internal offsets
V
OUT
IN
), the programmed offset DAC voltage (V
Offset
Offset
+
V
=
+
OS1
Equation 2: Offset DAC Output Voltage
Equation 3: LM9810 Offset Equation
Equation 4: LM9820 Offset Equation
V
x3 Boost
V
1V/V or
G
=
DAC
3V/V
IN
=
IN
B
Figure 4: Internal Offset Model
20LSBs (value in B4 - B0) PGA Gain
5LSBs (value in B4 - B0) PGA Gain
+
), the LM9810/20 internal offsets (V
B
V
=
, G
OS1
+
V
+
9.75mV (value in B4 - B0)
OS2
PGA
G
+
Offset
) and the analog channel gain con-
B
DAC
+
+
V
0.93V/V to
V
DAC
DAC
3V/V
G
PGA
PGA
+
V
V
+
OS2
http://www.national.com
+
OS3
G
PGA
ADC
DAC
OS1
), the pro-
+
V
OS1
, V
D
OUT
OS2
C
,