PCF8820U Philips Semiconductors, PCF8820U Datasheet - Page 28

• Manufacturer Part Number: PCF8820U
• Description: 67 x 101 Grey-scale/ECB colour dot matrix LCD driver
• Manufacturer: Philips Semiconductors

Philips Semiconductors
8.1.9
The voltage multiplier is in the direct drive mode
(V
It is recommended to always select the direct drive mode
before switching on the voltage multiplier. This is a feature
which can be used to reduce V
avoid high current when the voltage multiplier starts up.
Output V
bit PD = 1, bit DM = 0 and bit DOF = 0 or when bit DM = 0,
bit PD = 0 and bit HVE = 0.
Table 8 Output V
Note
1. X = don’t care.
8.1.10
The PCF8820 uses on-chip software to calibrate the frame
frequency. After reset, the frame frequency calibration is
disabled (bit OC = 0). Frame frequency calibration can
only be performed if the PCF8820 is not in Power-down
mode or in the partial screen mode.
The calibration is initiated by setting bit OC = 1 and is
stopped by setting bit OC = 0. The time between
calibration start and stop must be 190 s to give a frame
frequency of 77 Hz (typical value).
All other commands are allowed during a calibration.
The frame frequency calibration uses a pre-divider which
has a range from 1 : 1 to 1 : 15. The default ratio after reset
is 1 : 4. The calibration period determines the pre-divider
ratio for the oscillator frequency or external clock signal.
2000 Dec 07
DM
LCDOUT
If bit DM = 1 and Power-down mode (bit PD = 1)
If bit DM = 1 and display off mode (bit DOF = 1)
If bit DM = 1 and high voltage generator is disabled
(bit HVE = 0).
67 101 Grey-scale/ECB colour dot matrix
LCD driver
X
0
0
0
1
1
1
HVE
LCDOUT
D
F
= V
PD and DOF; note 1
X
X
X
X
0
0
1
RAME FREQUENCY CALIBRATION
IRECT DRIVE MODE
DD2
is high-impedance when bit DM = 0 and
PD
) in the following settings (see Table 8):
X
X
1
0
0
1
0
LCDOUT
DOF
X
X
1
0
0
1
0
as a function of bits DM, HVE,
high Z
high Z
high Z
V
V
V
internally generated V
LCDOUT
DD2
DD2
DD2
very quickly, or to
V
LCDOUT
LCD
28
The resulting frame frequency is calculated by the
equation:
where f
or an external clock signal source.
Figure 21 shows the resulting frame frequency at different
clock frequencies and at different pre-divider ratios, for a
calibration period of 190 s.
The frame frequency calibration can also be used to set
the frame frequency to a lower than typical value with a
corresponding reduction in current consumption. The
necessary calibration period (time between calibration
start and stop) can be estimated by the equation:
where t
desired frame frequency in Hz.
Figure 22 shows the resulting frame frequency as a
function of the calibration period at different pre-divider
ratios at a clock frequency of 336 kHz.
8.2
After power-on the content of all internal registers
including the DDRAM are in an undefined state. A reset
pulse must be applied within a specified time to reset all
internal registers. A reset can be achieved by applying an
external reset pulse (active LOW) to pad RES. When reset
occurs within the specified time all internal registers are
reset, however the DDRAM is still undefined.
After V
level must be 0.3V
(see Fig.24).
After reset the state of the PCF8820 is as follows:
t
cal
Default values of bits and registers as seen in Table 3
All row and column outputs are at V
V
RAM data is undefined.
LCDOUT
=
DD1
Reset and initialization
77 (Hz)
-------------------------------------------------
clk
cal
can be either the internal oscillator clock signal
f
is the calibration time in s and f
frame
has reached its minimum value, the RES input
is high-impedance
f
frame
=
190
-------------
1088
DD1
f
clk
after a maximum time t
s
pre-divider ratio Hz
Product specification
SS
PCF8820
(display off)
frame
su
is the