PCF8820U Philips Semiconductors, PCF8820U Datasheet - Page 16

• Manufacturer Part Number: PCF8820U
• Description: 67 x 101 Grey-scale/ECB colour dot matrix LCD driver
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.18.3
Thd system components are defined below (see Fig.13):
7.18.4
Each 8-bit data byte transferred over the bus must be
followed by an acknowledge bit (see Fig.14).
2000 Dec 07
handbook, full pagewidth
Transmitter: the device which sends data to the bus
Receiver: the device which receives data from the bus
Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
Slave: the device addressed by a master
Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
Synchronization: procedure to synchronize the clock
signals of two or more devices.
67 101 Grey-scale/ECB colour dot matrix
LCD driver
S
A
YSTEM CONFIGURATION
CKNOWLEDGE
SCL
SDA
BY TRANSMITTER
TRANSMITTER/
DATA OUTPUT
DATA OUTPUT
RECEIVER
BY RECEIVER
MASTER
SCL FROM
MASTER
condition
START
RECEIVER
S
Fig.14 Acknowledgement on the I
SLAVE
Fig.13 System configuration.
1
TRANSMITTER/
RECEIVER
SLAVE
16
During the acknowledge clock pulse a HIGH-level signal is
put on the bus by the transmitter.
A slave receiver which is addressed must generate an
acknowledge bit after the reception of each data byte.
A master receiver must generate an acknowledge bit after
receiving a data byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line to a LOW-level during the
acknowledge clock pulse. Set-up and hold times must be
taken into consideration to ensure that the SDA line is
stable during the HIGH period of the acknowledge related
clock pulse.
A master receiver must signal an end-of-data to the slave
transmitter by not generating an acknowledge bit on the
last byte that has been clocked out of the slave transmitter.
In this event the slave transmitter must leave the data line
HIGH to allow the master to generate a STOP condition.
For the PCF8820 the acknowledge bit is output at
pad SDA_OUT.
2
TRANSMITTER
2
C-bus.
MASTER
not acknowledge
acknowledge
8
acknowledgement
clock pulse for
TRANSMITTER/
RECEIVER
MASTER
9
MBC602
Product specification
MGA807
PCF8820