M48T08 ST Microelectronics, M48T08 Datasheet - Page 9

• Manufacturer Part Number: M48T08
• Description: 64 Kbit 8Kb x 8 TIMEKEEPER SRAM
• Manufacturer: ST Microelectronics

DESCRIPTION (cont’d)
The M48T08/18 also has its own Power-fail Detect
circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When V
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
eration brought on by low V
approximately 3V, the control circuitry connects the
battery which maintains data and clock operation
until valid power returns.
READ MODE
The M48T08/18 is in the Read Mode whenever W
(Write Enable) is high, E1 (Chip Enable 1) is low,
and E2 (Chip Enable 2) is high. The device archi-
tecture allows ripple-through access of data from
eight of 65,536 locations in the static storage array.
Thus, the unique address specified by the 13 Ad-
dress Inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be avail-
able at the Data I/O pins within Address Access
time (t
stable, providing that the E1, E2, and G access
times are also satisfied. If the E1, E2 and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access times (t
or t
Table 11. Register Map
Keys: S = SIGN Bit
E2HQV
Address
1FFEh
1FFDh
1FFCh
1FFBh
1FFFh
1FFAh
1FF9h
1FF8h
FT = FREQUENCY TEST Bit (Set to ’0’ for normal clock operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0
AVQV
= Must be set to ’0’
CC
) or Output Enable Access time (t
) after the last address input signal is
is out of tolerance, the circuit write
D7
ST
W
0
0
0
0
0
D6
FT
R
0
0
0
CC
10 Years
. As V
10 Seconds
10 Minutes
D5
0
0
S
CC
10 Hours
10 Date
falls below
10 M.
GLQV
D4
0
E1LQV
Data
).
D3
0
The state of the eight three-state Data I/O signals
is controlled by E1, E2 and G. If the outputs are
activated before t
to an indeterminate state until t
Inputs are changed while E1, E2 and G remain
active, output data will remain valid for Output Data
Hold time (t
next Address Access.
WRITE MODE
The M48T08/18 is in the Write Mode whenever W,
E1, and E2 are active. The start of a write is
referenced from the latter occurring falling edge of
W or E1, or the rising edge of E2. A write is
terminated by the earlier rising edge of W or E1, or
the falling edge of E2. The addresses must be held
valid throughout the cycle. E1 or W must return high
or E2 low for a minimum of t
Chip Enable or t
initiation of another read or write cycle. Data-in
must be valid t
remain valid for t
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on E1 and G and a high on E2, a low on W will
disable the outputs t
Calibration
D2
Seconds
Minutes
Month
Hours
Date
Year
AXQX
Day
D1
DVWH
WHAX
) but will go indeterminate until the
WHDX
AVQV
WLQZ
D0
from Write Enable prior to the
prior to the end of write and
, the data lines will be driven
afterward. G should be kept
after W falls.
E1HAX
Seconds
M48T08, M48T18
Minutes
Function/Range
AVQV
Control
Month
Hour
Year
Date
BCD Format
Day
. If the Address
or t
E2LAX
00-99
01-12
01-31
01-07
00-23
00-59
00-59
from
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