CY7C1480V33 Cypress Semiconductor, CY7C1480V33 Datasheet

CY7C1480V33

Manufacturer Part Number

CY7C1480V33

Description

(CY7C1480V33 / CY7C1482V33 / CY7C1486V33) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Manufacturer

Cypress Semiconductor

Datasheet

1.CY7C1480V33.pdf (30 pages)

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Part Number

Manufacturer

Quantity

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Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY7C1480V33-167AXC

Manufacturer:

CYPRESS

Quantity:

101

Company:

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Part Number:

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Cypress Semiconductor Corp

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10 000

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1480V33-167AXCT

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY7C1480V33-167AXI

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ALTERA

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101

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1480V33-167BZI

Manufacturer:

Cypress Semiconductor Corp

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10 000

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY7C1480V33-200AXC

Manufacturer:

Cypress Semiconductor Corp

Quantity:

135

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1480V33-200AXC

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

CY7C1480V33-200AXCT

Manufacturer:

Cypress Semiconductor Corp

Quantity:

10 000

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY7C1480V33-250BZI

Manufacturer:

CYPRESS

Quantity:

101

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Cypress Semiconductor Corporation

Document #: 38-05283 Rev. *C

Features

Selection Guide

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

Shaded areas contain advance information.

Please contact your local Cypress sales representative for availability of these parts.

Note:

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200,167 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

• 2.5V / 3.3V I/O operation

• Fast clock-to-output times

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• CY7C1480V33 and CY7C1482V33 offered in

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

— 3.0 ns (for 250-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.4 ns (for 167-MHz device)

Pentium

JEDEC-standard lead-free 100-pin TQFP, 165-Ball fBGA

packages. CY7C1486V33 available in 209-Ball BGA

packages

interleaved or linear burst sequences

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined

•

3901 North First Street

PRELIMINARY

Functional Description

The CY7C1480V33/CY7C1482V33/CY7C1486V33 SRAM

integrates 2,097,152 x 36/4,194,304 x 18,1,048,576 × 72

SRAM cells with advanced synchronous peripheral circuitry

and a two-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered Clock Input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

Chip Enable (CE

Enables (BW

Asynchronous inputs include the Output Enable (OE) and the

ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the byte write control inputs. GW when active

LOW causes all bytes to be written.

The CY7C1480V33/CY7C1482V33/CY7C1486V33 operates

from a +3.3V core power supply while all outputs may operate

with either a +2.5 or +3.3V supply. All inputs and outputs are

JEDEC-standard JESD8-5-compatible.

250 MHz

500

120

3.0

), Burst Control inputs (ADSC, ADSP, and ADV), Write

•

San Jose

, and BWE), and Global Write (GW).

200 MHz

), depth-expansion Chip Enables (CE

500

120

3.0

CA 95134

[1]

Revised December 3, 2004

167 MHz

450

120

3.4

Sync SRAM

CY7C1480V33

CY7C1482V33

CY7C1486V33

•

408-943-2600

Unit

and

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