M4T28-BR12SH ST Microelectronics, M4T28-BR12SH Datasheet - Page 13

• Manufacturer Part Number: M4T28-BR12SH
• Description: TIMEKEEPER SNAPHAT Battery & Crystal
• Manufacturer: ST Microelectronics

READ Mode
In this mode the master reads the M41ST85Y/W
slave after setting the slave address (see Figure
13, page 13). Following the WRITE Mode Control
Bit (R/W=0) and the Acknowledge Bit, the word
address 'An' is written to the on-chip address
pointer. Next the START condition and slave ad-
dress are repeated followed by the READ Mode
Control Bit (R/W=1). At this point the master trans-
mitter becomes the master receiver.
The data byte which was addressed will be trans-
mitted and the master receiver will send an Ac-
knowledge Bit to the slave transmitter. The
address pointer is only incremented on reception
of an Acknowledge Clock. The M41ST85Y/W
slave transmitter will now place the data byte at
address An+1 on the bus, the master receiver
reads and acknowledges the new byte and the ad-
dress pointer is incremented to An+2.
Figure 13. Slave Address Location
Figure 14. READ Mode Sequence
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
S
ADDRESS
SLAVE
DATA n+X
START
ADDRESS (An)
WORD
P
1
1
SLAVE ADDRESS
S
0
ADDRESS
SLAVE
1
This cycle of reading consecutive addresses will
continue until the master receiver sends a STOP
condition to the slave transmitter (see Figure 14,
page 13).
The system-to-user transfer of clock data will be
halted whenever the address being read is a clock
address (00h to 07h). The update will resume ei-
ther due to a Stop Condition or when the pointer
increments to a non-clock or RAM address.
Note: This is true both in READ Mode and WRITE
Mode.
An alternate READ Mode may also be implement-
ed whereby the master reads the M41ST85Y/W
slave without first writing to the (volatile) address
pointer. The first address that is read is the last
one stored in the pointer (see Figure 15, page 14).
0
0
0
R/W
DATA n
A
AI00602
M41ST85Y, M41ST85W
DATA n+1
AI00899
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