M4T28-BR12SH ST Microelectronics, M4T28-BR12SH Datasheet - Page 10

• Manufacturer Part Number: M4T28-BR12SH
• Description: TIMEKEEPER SNAPHAT Battery & Crystal
• Manufacturer: ST Microelectronics

M41ST85Y, M41ST85W
OPERATING MODES
The M41ST85Y/W clock operates as a slave de-
vice on the serial bus. Access is obtained by im-
plementing a start condition followed by the
correct slave address (D0h). The 64 bytes con-
tained in the device can then be accessed sequen-
tially in the following order:
1. Tenths/Hundredths of a Second Register
2. Seconds Register
3. Minutes Register
4. Century/Hours Register
5. Day Register
6. Date Register
7. Month Register
8. Year Register
9. Control Register
10. Watchdog Register
11 - 16. Alarm Registers
17 - 19. Reserved
20. Square Wave Register
21 - 64. User RAM
The M41ST85Y/W clock continually monitors V
for an out-of-tolerance condition. Should V
below V
progress and resets the device address counter.
Inputs to the device will not be recognized at this
time to prevent erroneous data from being written
to the device from a an out-of-tolerance system.
When V
cally switches over to the battery and powers
down into an ultra low current mode of operation to
10/33
PFD
CC
falls below V
, the device terminates an access in
SO
, the device automati-
CC
fall
CC
conserve battery life. As system power returns and
V
and the power supply is switched to external V
Write protection continues until V
V
For more information on Battery Storage Life refer
to Application Note AN1012.
2-Wire Bus Characteristics
The bus is intended for communication between
different ICs. It consists of two lines: a bi-direction-
al data signal (SDA) and a clock signal (SCL).
Both the SDA and SCL lines must be connected to
a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the bus
– During data transfer, the data line must remain
– Changes in the data line, while the clock line is
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
CC
PFD
is not busy.
stable whenever the clock line is High.
High, will be interpreted as control signals.
rises above V
(min) plus t
REC
SO
(min).
, the battery is disconnected,
CC
reaches
CC
.