IDT71T75602 Integrated Device Technology, IDT71T75602 Datasheet - Page 11

• Manufacturer Part Number: IDT71T75602
• Description: 512K x 36/ 1M x 18 2.5V Synchronous ZBT SRAMs 2.5V I/O/ Burst Counter Pipelined Outputs
• Manufacturer: Integrated Device Technology

NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Cycle
Cycle
n+2
n+3
n+4
n+5
n+6
n+7
n+2
n+3
n+4
n+5
n+6
n+7
n+1
n+1
n
n
Address
Address
A
A
A
A
A
A
A
A
A
A
X
X
X
X
X
X
0
2
3
4
0
2
3
4
1
1
1
1
= L, CE
= L, CE
R/
R/
H
X
H
X
X
H
H
H
X
X
X
L
L
L
L
L
2
2
= L and CE
= L and CE
ADV/
ADV/
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
2
2
= H. CE = H is defined as CE
= H. CE = H is defined as CE
X
X
X
X
X
X
L
L
L
L
L
L
L
L
L
L
(2)
(2)
L
H
L
H
H
L
L
L
L
H
L
H
H
L
L
L
6.42
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
11
x
x
1
1
= H, CE
= H, CE
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
2
2
= H or CE
= H or CE
I/O
I/O
Q
Q
Q
Q
D
D
Q
D
X
X
X
X
X
X
X
X
0
2
Commercial and Industrial Temperature Ranges
0
0
0
2
1
1
2
2
= L.
= L.
Comments
Clock n+1 Ignored
Clock Valid
Clock Ignored. Data Q
Clock Ignored. Data Q
Comments
Clock n+1 Ignored.
Clock Valid.
Clock Ignored.
Clock Ignored.
Address and Control meet setup
Address A
Address A
Address A
Address and Control meet setup.
Write Data D
Write Data D
Write Data D
0
1
2
Read out (bus trans.)
Read out (bus trans.)
Read out (bus trans.)
0
1
2
0
0
is on the bus.
is on the bus.
5313 tbl 17
5313 tbl 18