IDT71T016 Integrated Device Technology, IDT71T016 Datasheet - Page 6

• Manufacturer Part Number: IDT71T016
• Description: LOW POWER 2V CMOS SRAM 1 MEG (64K x 16-BIT)
• Manufacturer: Integrated Device Technology

IDT71T016
LOW POWER 2V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
NOTES:
1.
2. Address must be valid prior to or coincident with the later of
3. Transition is measured 200mV from steady state.
NOTES:
1.
2. A write occurs during the overlap of a LOW
3.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
6. Transition is measured 200mV from steady state.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
TIMING WAVEFORM OF READ CYCLE NO. 2
ADDRESS
ADDRESS
BHE
BHE
DATA
WE
WE
OE
off and data to be placed on the bus for the required t
minimum write pulse is as short as the specified t
DATA
DATA
is continuously HIGH. If during a
or (
is HIGH for Read Cycle.
,
,
CS
BLE
BLE
OUT
CS
WE
OUT
BHE
OE
CS
LOW or
IN
and
BLE
BHE
) or
and
PREVIOUS DATA VALID
CS
BLE
must be HIGH during all address transitions.
LOW transition occurs simultaneously with or after the
WE
t
AS
controlled write cycle
CS
, LOW
t
WP
CLZ
.
DW
(4)
BHE
(3)
. If
t
WHZ
t
ACS
or
t
t
CS
OE
BLZ
AA
t
AW
BLE
OE
(6)
t
t
,
(2)
BE
CW
is HIGH during a
BHE
(3)
t
is LOW, t
OLZ
, and a LOW
(2)
(3)
t
t
BW
WC
(1)
t
, or
RC
(3)
WE
WE
t
BLE
OE
WP
t
WP
must be greater than or equal to t
CONTROLLED TIMING)
transition LOW; otherwise t
WE
WE
.
WE
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DATA
controlled write cycle, this requirement does not apply and the
t
DW
LOW transition, the outputs remain in a high-impedance state.
IN
VALID
DATA
t
t
DH
t
OW
WR
AA
OUT
(6)
is the limiting parameter.
WHZ
VALID
t
OH
t
t
CHZ
BHZ
+ t
(1,2,3,5)
t
OHZ
DW
(3)
(3)
to allow the I/O drivers to turn
(3)
DATA VALID
t
t
CHZ
BHZ
(6)
(6)
3777 drw 07
3777 drw 08
6