74HC03 Philips, 74HC03 Datasheet
74HC03
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74HC03 Summary of contents
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DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT03 Quad 2-input NAND gate Product specification File under Integrated Circuits, IC06 ...
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... Philips Semiconductors Quad 2-input NAND gate FEATURES Level shift capability Output capability: standard (open drain) I category: SSI CC GENERAL DESCRIPTION The 74HC/HCT03 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no ...
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... Philips Semiconductors Quad 2-input NAND gate PIN DESCRIPTION PIN NO. SYMBOL 10 GND Fig.1 Pin configuration. Fig.4 Functional diagram. December 1990 NAME AND FUNCTION data inputs data inputs data outputs ground (0 V) positive supply voltage Fig ...
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... Philips Semiconductors Quad 2-input NAND gate RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND (ground = 0 V) SYMBOL PARAMETER V DC supply voltage output voltage input diode current output diode current output sink current ...
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... Philips Semiconductors Quad 2-input NAND gate DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” not valid for open drain. They are replaced by I Output capability: standard (open drain), excepting V I category: SSI CC Voltages are referenced to GND (ground = 0 V) SYMBOL PARAMETER min ...
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... Philips Semiconductors Quad 2-input NAND gate DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” not valid for open drain. They are replaced by I Output capability: standard (open drain), excepting V I category: SSI CC Voltages are referenced to GND (ground = 0 V) SYMBOL PARAMETER min ...
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... Philips Semiconductors Quad 2-input NAND gate AC WAVEFORMS HC 50 GND HCT 1 GND Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times. TEST CIRCUIT AND WAVEFORMS Fig.7 Test circuit (open drain) Definitions for Figs ...
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... Philips Semiconductors Quad 2-input NAND gate APPLICATION INFORMATION (a) (1) V ( (2) V ( (3) V ( (4) V ( Fig.10 Minimum resistive load as a function of the pull-up voltage. Notes to Figs 9 and (R) 0 positive current will flow into the receiver (as described in the “USER GUIDE ”; input/output ...