74HC/HCT139 Philips Semiconductors (Acquired by NXP), 74HC/HCT139 Datasheet
74HC/HCT139
Related parts for 74HC/HCT139
74HC/HCT139 Summary of contents
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... DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT139 Dual 2-to-4 line decoder/demultiplexer Product specification File under Integrated Circuits, IC06 INTEGRATED CIRCUITS ...
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... ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information” September 1993 GENERAL DESCRIPTION The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers ...
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... V CC Fig.1 Pin configuration. (a) September 1993 NAME AND FUNCTION enable inputs (active LOW) address inputs outputs (active LOW) ground (0 V) outputs (active LOW) address inputs positive supply voltage Fig.2 Logic symbol. Fig.3 IEC logic symbol. 3 Product specification 74HC/HCT139 (b) ...
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... Notes HIGH voltage level L = LOW voltage level X = don’t care Fig.5 Logic diagram (one decoder/demultiplexer). September 1993 OUTPUTS Product specification 74HC/HCT139 ...
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... Product specification 74HC/HCT139 . TEST CONDITIONS UNIT WAVEFORMS 125 (V) min. max. 220 2 4.5 Fig.6 38 6.0 205 2 4.5 Fig.7 35 6.0 110 2 4.5 Figs 6 and ...
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... CC COEFFICIENT amb 74HCT min. typ. max. min. max Product specification 74HC/HCT139 . TEST CONDITIONS UNIT WAVEFORMS 125 (V) min. max 4.5 Fig 4.5 Fig 4.5 Figs 6 and 7 ...
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... GND Fig.7 Waveforms showing the enable input (nE) to output (nY times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines” September 1993 ) to output (nY ) propagation delays and the output transition propagation delays and the output transition Product specification 74HC/HCT139 ...