MM74HCT374 Fairchild, MM74HCT374 Datasheet

no-image

MM74HCT374

Manufacturer Part Number
MM74HCT374
Description
3-STATE Octal D-Type Latch . 3-STATE Octal D-Type Flip-Flop
Manufacturer
Fairchild
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MM74HCT374N
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
© 1999 Fairchild Semiconductor Corporation
MM74HCT373WM
MM74HCT373SJ
MM74HCT373MTC
MM74HCT373N
MM74HCT373WM
MM74HCT373SJ
MM74HCT373MTC
MM74HCT373N
MM74HCT373 • MM74HCT374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
The
MM74HCT374 Octal D-type flip flops advanced silicon-
gate CMOS technology, which provides the inherent bene-
fits of low power consumption and wide power supply
range, but are LS-TTL input and output characteristic &
pin-out compatible. The 3-STATE outputs are capable of
driving 15 LS-TTL loads. All inputs are protected from dam-
age due to static discharge by internal diodes to V
ground.
When the MM74HCT373 LATCH ENABLE input is HIGH,
the Q outputs will follow the D inputs. When the LATCH
ENABLE goes LOW, data at the D inputs will be retained at
the outputs until LATCH ENABLE returns HIGH again.
When a high logic level is applied to the OUTPUT CON-
TROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.
The MM74HCT374 are positive edge triggered flip-flops.
Data at the D inputs, meeting the setup and hold time
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number
MM74HCT373
Package Number
MTC20
MTC20
octal
M20B
M20D
M20B
M20D
N20A
N20A
D-type
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
DS005367.prf
latches
CC
and
and
requirements, are transferred to the Q outputs on positive
going transitions of the CLOCK (CK) input. When a high
logic level is applied to the OUTPUT CONTROL (OC)
input, all outputs go to a high impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Features
TTL input characteristic compatible
Typical propagation delay: 20 ns
Low input current: 1 A maximum
Low quiescent current: 80 A maximum
Compatible with bus-oriented systems
Output drive capability: 15 LS-TTL loads
Package Descriptions
February 1984
Revised February 1999
www.fairchildsemi.com

Related parts for MM74HCT374

MM74HCT374 Summary of contents

Page 1

... TROL input, all outputs high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74HCT374 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time Ordering Code: Order Number ...

Page 2

... HIGH Level L LOW Level Q Level of output before steady-state input conditions were established High Impedance www.fairchildsemi.com Top View MM74HCT374 MM74HCT374 373 Output Clock Output Control HIGH Level L LOW Level X Don’t Care ...

Page 3

... Logic Diagrams MM74HCT373 MM74HCT374 3 www.fairchildsemi.com ...

Page 4

... Output Leakage Enable Current I Maximum Quiescent Supply Current OUT V 2.4V or 0.5V (Note 4) IN Note 4: Measured per pin. All others tied ground. CC www.fairchildsemi.com Recommended Operating (Note 1) Conditions 0.5 to 7.0V 1 1.5V Supply Voltage ( 0 0.5V DC Input or Output Voltage ...

Page 5

... Guaranteed Units Limit 125 C A Units www.fairchildsemi.com ...

Page 6

... Maximum Disable Propagation Delay PHZ PLZ Control to Output t Minimum Clock Pulse Width W t Minimum Setup Time Data to Clock S t Minimum Hold Time Clock to Data H AC Electrical Characteristics MM74HCT374: V 5.0V 10 (unless otherwise specified Symbol Parameter f Maximum Clock Frequency MAX t ...

Page 7

... Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20B Package Number M20D 7 www.fairchildsemi.com ...

Page 8

... Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC20 8 ...

Page 9

... Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. Package Number N20A 2 ...

Related keywords