MM74HC540 Fairchild, MM74HC540 Datasheet

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MM74HC540

Manufacturer Part Number
MM74HC540
Description
Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer
Manufacturer
Fairchild
Datasheet

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© 1999 Fairchild Semiconductor Corporation
MM74HC540WM
MM74HC540SJ
MM74HC540MTC
MM74HC540N
MM74HC541WM
MM74HC541SJ
MM74HC541MTC
MM74HC541N
MM74HC540 • MM74HC541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HC540 and MM74HC541 3-STATE buffers uti-
lize advanced silicon-gate CMOS technology. They pos-
sess high drive current outputs which enable high speed
operation even when driving large bus capacitances.
These circuits achieve speeds comparable to low power
Schottky devices, while retaining the advantage of CMOS
circuitry, i.e., high noise immunity, and low power consump-
tion. Both devices have a fanout of 15 LS-TTL equivalent
inputs.
The MM74HC540 is an inverting buffer and the
MM74HC541 is a non-inverting buffer. The 3-STATE con-
trol gate operates as a two-input NOR such that if either G1
or G2 are HIGH, all eight outputs are in the high-imped-
ance state.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Order Number
Package Number
MM74HC540
MTC20
MTC20
Top View
M20D
M20D
M20B
M20B
N20A
N20A
Pin Assignments for DIP, SOIC, SOP and TSSOP
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
DS005341.prf
In order to enhance PC board layout, the MM74HC540 and
MM74HC541 offers a pinout having inputs and outputs on
opposite sides of the package. All inputs are protected from
damage due to static discharge by diodes to V
ground.
Features
Typical propagation delay: 12 ns
3-STATE outputs for connection to system buses
Wide power supply range: 2–6V
Low quiescent current: 80 A maximum (74HC Series)
Output current: 6 mA
Package Description
MM74HC541
Top View
September 1983
Revised February 1999
www.fairchildsemi.com
CC
and

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MM74HC540 Summary of contents

Page 1

... Pin Assignments for DIP, SOIC, SOP and TSSOP Top View MM74HC540 © 1999 Fairchild Semiconductor Corporation In order to enhance PC board layout, the MM74HC540 and MM74HC541 offers a pinout having inputs and outputs on opposite sides of the package. All inputs are protected from damage due to static discharge by diodes to V ground ...

Page 2

... Note 4: For a power supply of 5V 10% the worst case output voltages (V designing with this supply. Worst case V and V occur rent ( and I ) occur for CMOS at the higher voltage and so the 6.0V values should be used www.fairchildsemi.com Recommended Operating (Note 1) Conditions 0.5 to 7.0V 1 1.5V Supply Voltage ( 0 0.5V ...

Page 3

... Guaranteed Units Limit 125 C A Units 149 ns 224 171 ns 246 224 ns 298 224 www.fairchildsemi.com ...

Page 4

... Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20B Package Number M20D 4 ...

Page 5

... Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 5 www.fairchildsemi.com ...

Page 6

... Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. Package Number N20A 2 ...

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