W83194R-17A Winbond, W83194R-17A Datasheet - Page 4

no-image

W83194R-17A

Manufacturer Part Number
W83194R-17A
Description
100MHZ AGP CLOCK FOR SIS CHIPSET
Manufacturer
Winbond
Datasheet
5.2 CPU, SDRAM, PCI Clock Outputs, continued
PCICLK 0 / *FS2
PCICLK [ 1:4 ]
5.3 I
SDATA
SDCLK
5.4 Fixed Frequency Outputs
REF0 / CPU3.3#_2.5
REF1
24MHz / *MODE
48MHz / *FS0
2
C Control Interface
SYMBOL
SYMBOL
SYMBOL
10,11,12,13
PIN
PIN
PIN
23
24
46
25
26
8
2
OUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
- 4 -
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
PCI clock during normal operation.
Low skew (< 250ps) PCI clock outputs.
Serial data of I
Serial clock of I
Internal 250k
Latched input for CPU3.3#_2.5 at initial power up.
Reference clock during normal operation.
Latched high - Vddq2b = 2.5V
Latched low - Vddq2b = 3.3V
Internal 250k
Internal 250k
Latched input for MODE at initial power up. 24MHz
output for super I/O during normal operation.
Internal 250k
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks. 48MHz output for USB during normal
operation.
2
pull-up.
pull-up.
pull-up.
pull-up.
C 2-wire control interface
2
C 2-wire control interface
Publication Release Date: Sep. 1998
W83194R-17/-17A
FUNCTION
FUNCTION
FUNCTION
PRELIMINARY
Revision 0.20

Related parts for W83194R-17A