W83194R-17A Winbond, W83194R-17A Datasheet - Page 2

• Manufacturer Part Number: W83194R-17A
• Description: 100MHZ AGP CLOCK FOR SIS CHIPSET
• Manufacturer: Winbond

3.0 BLOCK DIAGRAM
4.0 PIN CONFIGURATION
CPU_STOP#/SDRAM11
PCI_STOP#/SDRAM10
REF0/CPU3.3#_2.5
CPU_STOP#
CPU3.3#_2.5
PCI_STOP#
PCICLK_F/*FS1
PCICLK0/*FS2
FS(0:2)
SDATA
MODE
SCLK
X1
X2
SDRAM 9
SDRAM 8
PCICLK2
PCICLK3
PCICLK4
PCICLK1
SDATA
SDCLK
Vddq3
Vddq3
Vddq3
3
AGP0
Vss
Vdd
Vss
Xout
Vss
Vss
Xin
PLL2
Spectrum
POR
XTAL
OSC
Spread
PLL1
LATCH
~
Control
Config.
Logic
Reg.
~
14
16
21
10
11
12
13
15
17
18
19
20
22
23
24
7
1
2
3
4
6
9
5
8
5
- 2 -
¡Ò 2
PCI
clock
Divder
STOP
STOP
STOP
33
32
31
30
29
28
27
26
25
48
47
46
45
43
42
41
40
39
37
35
34
38
36
44
Publication Release Date: Sep. 1998
W83194R-17/-17A
2
12
3
4
5
2
SDRAM 1
48MHz/*FS0
24MHz/*MODE
Vddq2
CPUCLK2
CPUCLK3
SDRAM 0
SDRAM 2
SDRAM 3
SDRAM 4
SDRAM 5
Vddq3
SDRAM 6
SDRAM 7
Vss
AGP1
REF1
CPUCLK0
Vss
Vddq3
Vss
Vss
CPUCLK1
Vddq2b
48MHz
24MHz
AGP(0:1)
SDRAM(0:11)
REF(0:1)
CPUCLK(0:3)
PCICLK(0:4)
PCICLK_F
PRELIMINARY
Revision 0.20