IS62WV12816 ISSI, IS62WV12816 Datasheet - Page 9

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IS62WV12816

Manufacturer Part Number
IS62WV12816
Description
128K x 16 LOW VOLTAGE ULTRA LOW POWER CMOS STATIC RAM
Manufacturer
ISSI
Datasheet

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IS62WV12816ALL,
WRITE CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. E
06/08/05
Symbol
t
t
t
t
t
t
t
t
t
t
t
and output loading specified in Figure 1.
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
WC
SCS1/
AW
HA
SA
PWB
PWE
SD
HD
HZWE
LZWE
(3)
t
(3)
SCS2
Parameter
Write Cycle Time
CS1/CS2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
LB, UB Valid to End of Write
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
IS62WV12816BLL
Min.
45
35
35
35
35
20
0
0
0
5
1-800-379-4774
45ns
Max.
20
(1,2)
(Over Operating Range)
Min.
55
45
45
45
40
25
0
0
0
5
55 ns
Max.
20
Min.
70
60
60
60
30
50
0
0
0
5
70 ns
Max.
20
ISSI
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
9

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