CY7C1370C Cypress, CY7C1370C Datasheet - Page 14

• Manufacturer Part Number: CY7C1370C
• Description: 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
• Manufacturer: Cypress

Document #: 38-05233 Rev. *D
TAP AC Switching Characteristics
TAP Timing and Test Conditions
Set-up Times
t
t
t
Hold Times
t
t
t
Output Times
t
t
TMSS
TDIS
CS
TMSH
TDIH
CH
TDOV
TDOX
Parameter
TDO
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after clock rise
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
Z
Test Mode Select
TMS
Test Clock
TCK
Test Data-In
TDI
Test Data-Out
TDO
0
= 50Ω
(a)
1.25V for 2.5V V
GND
C
50Ω
L
= 20 pF
DDQ
Over the Operating Range
Description
t
TMSS
t
TDIS
t
TH
V
t
TDOV
t
SS
TL
[12, 13]
t
t
TMSH
TDIH
1.5 ns
(continued)
2.5V
t
TCYC
t
TDOX
ALL INPUT PULSES
1.25V
Min.
10
10
10
10
10
10
0
CY7C1370C
CY7C1372C
1.5 ns
Max.
20
Page 14 of 27
Unit
ns
ns
ns
ns
ns
ns
ns
ns