CY7C1049CV33-10VI Cypress Semiconductor, CY7C1049CV33-10VI Datasheet - Page 4

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CY7C1049CV33-10VI

Manufacturer Part Number
CY7C1049CV33-10VI
Description
512K x 8 Static RAM
Manufacturer
Cypress Semiconductor
Datasheet
Document #: 38-05006 Rev. *B
Switching Waveforms
Read Cycle No. 2 (OE Controlled)
Write Cycle No. 1(WE Controlled, OE HIGH During Write)
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high-impedance if OE = V
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
17. During this period the I/Os are in the output state and input signals should not be applied.
DATA OUT
ADDRESS
ADDRESS
CURRENT
DATA I/O
SUPPLY
CE
CE
WE
V
OE
OE
CC
NOTE 17
HIGH IMPEDANCE
t
PU
(continued)
t
LZCE
IH
t
SA
.
t
HZOE
[13, 14]
t
t
ACE
LZOE
50%
t
DOE
t
AW
t
t
RC
SCE
[15, 16]
t
WC
DATA
t
t
PWE
SD
IN
DATA VALID
VALID
t
HZOE
t
HA
t
HD
t
HZCE
CY7C1049CV33
t
PD
50%
IMPEDANCE
HIGH
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I
I
CC
SB

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