MT4C1M16E5 Micron Technology, MT4C1M16E5 Datasheet - Page 4

• Manufacturer Part Number: MT4C1M16E5
• Description: EDO DRAM
• Manufacturer: Micron Technology

However, an EARLY WRITE on one byte and a LATE
WRITE on the other byte, after a CAS# precharge has
been satisfied, are permissible.
DRAM REFRESH
power and executing any RAS# cycle (READ, WRITE) or
RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN)
so that all 1,024 combinations of RAS# addresses are
executed within
The CBR, EXTENDED and SELF REFRESH cycles will
invoke the internal refresh counter for automatic RAS#
addressing.
version. The self refresh feature is initiated by per-
forming a CBR REFRESH cycle and holding RAS# LOW
for the specified
the choice of a fully static, low-power data retention
mode or a dynamic refresh mode at the extended re-
fresh period of 128ms, or 125µs per row, when using a
1 Meg x 16 EDO DRAM
D52_B.p65 – Rev. B; Pub. 3/01
Preserve correct memory cell data by maintaining
An optional self refresh mode is available on the “S”
LOWER BYTE
UPPER BYTE
(DQ8-DQ15)
(DQ0-DQ7)
t
OF WORD
OF WORD
t
RASS. The “S” option allows the user
REF (MAX), regardless of sequence.
CASH#
CASL#
RAS#
WE#
STORED
X = NOT EFFECTIVE (DON'T CARE)
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
WORD and BYTE WRITE Example
INPUT
DATA
0
0
1
0
0
0
0
0
X
X
X
X
X
X
X
X
ADDRESS 0
WORD WRITE
INPUT
DATA
1
0
1
0
1
1
1
1
Figure 3
STORED
DATA
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
4
STORED
distributed CBR REFRESH. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.
RAS# HIGH for a minimum time of
allows for the completion of any internal refresh cycles
that may be in process at the time of the RAS# LOW-to-
HIGH transition. If the DRAM controller uses a distrib-
uted refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con-
troller utilizes a RAS#-ONLY or burst refresh sequence,
all 1,024 rows must be refreshed within the average
internal refresh rate, prior to the resumption of normal
operation.
STANDBY
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
DATA
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
The self refresh mode is terminated by driving
Returning RAS# and CAS# HIGH terminates a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
LOWER BYTE WRITE
INPUT
DATA
ADDRESS 1
1
1
0
1
1
1
1
1
X
X
X
X
X
X
X
X
INPUT
DATA
16Mb: 1 MEG x16
STORED
DATA
1
1
0
1
1
1
1
1
1
0
1
0
1
1
1
1
EDO DRAM
t
RPS. This delay
©2001, Micron Technology, Inc