AD7476ART Analog Devices, AD7476ART Datasheet - Page 5

• Manufacturer Part Number: AD7476ART
• Description: 1 MSPS/ 12-/10-/8-Bit ADCs in 6-Lead SOT-23
• Manufacturer: Analog Devices

TIMING SPECIFICATIONS
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
6
7
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
(T
V
Analog Input Voltage to GND . . . . . . . –0.3 V to V
Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V
Digital Output Voltage to GND . . . . . –0.3 V to V
Input Current to Any Pin Except Supplies
Operating Temperature Range
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
SOT-23 Package, Power Dissipation . . . . . . . . . . . . . 450 mW
Lead Temperature, Soldering
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kV
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7476/AD7477/AD7478 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
SCLK
A Version timing specifications apply to the AD7477 S Version; B Version timing specifications apply to the AD7476 S Version.
3 V specifications apply from V
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
t
See Power-up Time section.
CONVERT
QUIET
1
2
3
4
5
6
7
8
POWER-UP
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
V
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
8
5
5
6
DD
θ
DD
A
Commercial (A, B Version) . . . . . . . . . . . . –40°C to +85°C
Military (S Version) . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
θ
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
JC
= 25°C unless otherwise noted)
JA
= 4.75 V to 5.25 V.
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
4
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 92°C/W
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 230°C/W
7
3 V
10
20
12
16 × t
50
10
10
20
40
70
0.4 t
0.4 t
10
10
25
1
AD7476/AD7477/AD7478
3
SCLK
SCLK
Limit at T
SCLK
DD
= 2.7 V to 3.6 V for A Version; 3 V specifications apply from V
MIN
, T
5 V
10
20
12
16 × t
50
10
10
20
20
20
0.4 t
0.4 t
10
10
25
1
1, 2
1
MAX
3
SCLK
SCLK
2
SCLK
(V
DD
. . . . . . . ± 10 mA
= 2.35 V to 5.25 V; T
DD
DD
Unit
kHz min
MHz max
MHz max
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs typ
+ 0.3 V
+ 0.3 V
A
= T
NOTES
1
2
Stresses above those listed under Absolute Maximum Ratings may cause perma-
Transient currents of up to 100 mA will not cause SCR latch-up.
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
MIN
Description
A Version
B Version
Minimum Quiet Time Required Between Bus Relinquish and
Start of Next Conversion
Minimum CS Pulsewidth
CS to SCLK Setup Time
Delay from CS Until SDATA Three-State Disabled
Data Access Time After SCLK Falling Edge. A Version
Data Access Time After SCLK Falling Edge. B Version
SCLK Low Pulsewidth
SCLK High Pulsewidth
SCLK to Data Valid Hold Time
SCLK Falling Edge to SDATA High Impedance
SCLK Falling Edge to SDATA High Impedance
Power-Up Time from Full Power-Down
to T
MAX
DD
, unless otherwise noted.)
= 2.35 V to 3.6 V for B Version; 5 V specifications apply from
8
, quoted in the timing characteristics is the true bus relinquish
TO OUTPUT
PIN
AD7476/AD7477/AD7478
DD
) and timed from a voltage level of 1.6 V.
50pF
C
L
200 A
200 A
WARNING!
I
I
OL
OH
ESD SENSITIVE DEVICE
1.6V