AD7243 Analog Devices, AD7243 Datasheet - Page 11

• Manufacturer Part Number: AD7243
• Description: LC2MOS 12-Bit Serial DACPORT
• Manufacturer: Analog Devices

Common clock, data, and synchronization signals are applied to
all DACs in the chain. The loading sequence starts by taking
SYNC low. The data is then clocked into the input registers on
the falling edge of SCLK. Sixteen clock pulses are required for
each DAC in the chain. The data ripples through the input reg-
isters with the first 16-bit word filling the last register in the
chain after 16N clock pulses where N = the total number of
DACs in the chain.
When valid data has been loaded into all the registers, the
SYNC input should be taken high and a common LDAC pulse
used to update all the DACs simultaneously.
APPLICATIONS
OPTO-ISOLATED INTERFACE
In many process control type applications it is necessary to pro-
vide an isolation barrier between the controller and the unit be-
ing controlled. Opto-isolators can provide voltage isolation in
excess of 3 kV. The serial loading structure of the AD7243
makes it ideal for opto-isolated interfaces as the number of in-
terface lines is kept to a minimum.
CONTROLLER
CONTROL OUT
CLOCK OUT
SYNC OUT
DATA OUT
QUAD OPTO-COUPLER
V
V
V
V
*ADDITIONAL PINS OMITTED FOR CLARITY
DD
DD
DD
DD
Figure 17 shows a 4-channel isolated interface using the
AD7243. The DCEN pin must be connected high to enable the
daisy-chain facility. Four channels with 12-bit resolution are
provided in the circuit shown, but this may be expanded to ac-
commodate any number of DAC channels without any extra
isolation circuitry.
The sequence of events to program the output channels is as
follows:
1. Take the SYNC line low.
2. Transmit the data as four 16-bit words. A total of 64 clock
3. Take the SYNC line high.
4. Pulse the LDAC line low. This updates all output channels
To reduce the number of opto-couplers, the LDAC line could
be driven from a one shot which is triggered by the rising edge
on the SYNC line. A low level pulse of 50 ns duration or greater
is all that is required to update the outputs.
pulses is required to clock the data through the chain.
simultaneously on the falling edge of LDAC.
SCLK
SYNC
LDAC
SCLK
SCLK
SYNC
LDAC
SYNC
LDAC
SYNC
LDAC
SCLK
AD7243*
AD7243*
AD7243*
AD7243*
SDO
SDIN
SDIN
SDO
SDIN
SDO
SDIN
SDO
DCEN
DCEN
DCEN
DCEN
V
V
V
V
OUT
OUT
OUT
OUT
V
V
V
V
DD
DD
DD
DD
V
V
V
V
OUT
OUT
OUT
OUT
(A)
(B)
(C)
(D)
AD7243