AD724 Analog Devices, AD724 Datasheet
AD724
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AD724 Summary of contents
Page 1
... V supply. No external delay lines or filters are required. The AD724 may be powered down when not in use. The AD724 accepts either FSC or 4FSC clock. When a clock is not available, a low cost parallel-resonant crystal (3.58 MHz (NTSC) or 4.43 MHz (PAL)) and the AD724’s on-chip oscilla- tor generate the necessary subcarrier clock ...
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... AD724–SPECIFICATIONS Parameter SIGNAL INPUTS (RIN, GIN, BIN) Input Amplitude 1 Black Level 2 Input Resistance Input Capacitance LOGIC INPUTS (HSYNC, VSYNC, FIN, ENCD, STND, SELECT) CMOS Logic Levels Logic LO Input Voltage Logic HI Input Voltage Logic LO Input Current (DC) Logic HI Input Current (DC) 3 VIDEO OUTPUTS ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD724 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... AD724 Pin Mnemonic Description 1 STND A Logical HIGH input selects NTSC encoding. A Logical LOW input selects PAL encoding. CMOS/TTL Logic Levels. 2 AGND Analog Ground Connection. 3 FIN FSC clock or parallel-resonant crystal, or 4FSC clock input. For NTSC: 3.579 545 MHz or 14.318 180 MHz. For PAL: 4.433 619 MHz or 17.734 480 MHz. ...
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... LINE PAL NO FILTERING SLOW CLAMP TO 0.00V @ 6.72 s 0.5 0.0 ASYNCHRONOUS FRAMES SELECTED : –0 Figure 3. Modulated Pulse and Bar, PAL REV. B Typical Performance Characteristics–AD724 +5V COMPOSITE SYNC TSG 300 AD724 COMPOSITE VIDEO RGB TO VIDEO NTSC/PAL RGB ENCODER 3 FIN 75 GENLOCK ...
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... AD724 Figure 6. 100% Color Bars on Vector Scope, NTSC Figure 7. 100% Color Bars on Vector Scope, PAL 1.0 APL = 12.0% 525 LINE NTSC SLOW CLAMP TO 0.00V @ 6.63 s 0.5 0.0 SYNCHRONOUS –0 Figure 8. Multipulse, NTSC 1.0 APL = 11.7% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00V @ 6.72 s 0.5 0.0 ASYNCHRONOUS FRAMES SELECTED : – ...
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... MAX = 0.00 pk–pk = 1.14 –0.53 –0.01 100ns 5TH 6TH MAX = 0.10 pk–pk = 0.42 0.04 0.10 H TIMING (PAL) LINE = 25 MAX = 0.70 pk–pk = 1.89 0.42 0.70 94ns AVERAGE 5TH 6TH –7– AD724 9.72 s 9.0 5.49 s CYCLES 4.59 s 33.8 IRE 39.7 IRE 124ns AVERAGE 256 Figure 12. Horizontal Timing, NTSC 5.59 s 2.28 s 4.60 s 102ns 293.5mV 256 Figure 13. Horizontal Timing, PAL 249.0mV ...
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... The bandwidths stated in the above discussion are the design target bandwidths for NTSC and PAL. The AD724’s 4FSC clock (either produced by the on-chip PLL or user supplied) drives a digital divide-by-four circuit to create the quadrature signals for modulation. The reference phase used for the U signal ...
Page 9
... The two sync inputs HSYNC and VSYNC drive an XNOR gate to create a CSYNC signal for the AD724. If the user produces a true composite sync signal, it can be input to the HSYNC pin while the VSYNC pin is held high. In either case the CSYNC ...
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... F VGA OUTPUT CONNECTOR Figure 15. Interfacing the AD724 to the (Interlaced) VGA Port transmitted. Each output requires a 220 F series capacitor to work with the 75 CRMA signal has information mostly up at the chroma fre- quency and can use a smaller capacitor if desired, but 220 F can be used to minimize the number of different components used in the design ...
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... The circuit selection can be driven by the STND signal that already drives Pin 1 to select between NTSC and PAL operation for the AD724. A schematic for such a circuit is shown in Figure 17. Each crys- tal ties directly to FIN (Pin 3) with one terminal and has the other terminal connected via a series diode to ground ...
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... The HIGH (+5 V) signal applied to R1 forward biases CR1 with approximately 450 A of current. This turns the diode “on” (low impedance with a forward voltage of approximately 0.6 V) and selects Y1 as the crystal to run the oscillator on the AD724. The bias across the diode does not affect the operation of the oscillator. ...
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... These cannot be used for clocking other devices. A low cost oscillator can be made to provide a CW clock that can be used to drive both the AD724 FIN and other devices in the system that require a clock at this frequency. In addition, the same technique can be used to make a clock signal at a 4FSC, which might be required by other devices and can also be used to drive the FIN pin of the AD724 ...
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... ICs. Synchronous vs. Asynchronous Operation The source of RGB video and synchronization used as an input to the AD724 in some systems is derived from the same clock signal as used for the AD724 subcarrier input (FIN). These systems are said to be operating synchronously. In systems where two different clock sources are used for these signals, the operation is called asynchronous ...
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... REV. B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Wide Body SOIC (R-16) 0.4133 (10.50) 0.3977 (10.00 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65 0.3937 (10.00) PIN 1 0.1043 (2.65) 0.050 (1.27) 0.0291 (0.74) BSC 0.0926 (2.35) 0.0098 (0.25) 8 0.0192 (0.49) SEATING 0 0.0125 (0.32) PLANE 0.0138 (0.35) 0.0091 (0.23) –15– AD724 45 0.0500 (1.27) 0.0157 (0.40) ...