UPC1862GS NEC, UPC1862GS Datasheet - Page 28

• Manufacturer Part Number: UPC1862GS
• Description: BURST LOCK CLOCK GENERATOR
• Manufacturer: NEC

Care Point for Planning of Application Circuit
1.
2.
3.
28
Video signal
input
0.01
F
Processing of V
Please isolate Chroma. V
directly supply of the block’s V
Application of no using Chroma pin
If you don’t use Chroma pin but use Sync pin on PC1862, you process pin 1 to pin 18 as follows.
Application of no using Sync pin
If you don’t use Sync pin but use Chroma pin on PC1862, you process pin 19 to pin 36 as follows. In this case, you
need to input a pin 24 with burst gate pulse from external.
In this application, you can’t use output of pin 20 to pin 23.
5 V
47 F
SCO
1
SSI
36
CV
Comp Sync Output
digital signal, etc
CSO VSSI HDF
Processing IC of
2
CC1
35
CC
pin
TINT
GND
V
3
34
DD
CC
CIN
4
from Sync. V
33
Open
DD
ACCF
.
HDO
5
32
5 V
CKO
0.01 F
HKO
6
0.01 F
31
CC
as follows. If you have external processing block of digital signal, don’t
CKF
SGND HSOF1
7
30
COUT APCF CGND SCOF1 SCOF2 SCOF3
8
CV
29
47 F
2.2 k
2
CC1
HSOF2
9
PC1862
28
PC1862
HSOF3 AFCF
10
Chroma (Pin 1 to pin 18)
27
Sync (Pin 19 to pin 36)
SGND
CGND
30
10
0.01 F 47 F
11
26
PC1862
12
SV
5 V
25
0.01 F
CV
3.3 k
CC
SV
25
14
CC2
BGPE NHSO CPO
13
CC
24
3.3 k
CV
14
23
CC2
CV
5 V
0 V
15
CV
CC3
15
(Don’t use)
22
CC3
Open
Burst Gate Input
VCOO DIVS ESCI
16
FIO
21
17
VSO
20
PC1862
18
N/P
19