SL34118D System Logic Semiconductor, SL34118D Datasheet - Page 6

• Manufacturer Part Number: SL34118D
• Description: Voice Switched Speakerphone Circuit
• Manufacturer: System Logic Semiconductor

SL34118
MICROPHONE AMPLIFIER
noninverting input internally connected to V
the inverting input and the output are pinned out.
Unlike most op-amps, the amplifier has an all-NPN
output stage, which maximizes phase margin and
gain-bandwidth. This feature ensures stability at
gains less than unity, as well as with a wide range of
reactive loads. The open loop gain is typically 80 dB
(f<100 Hz), and the gain-bandwidth is typically
1.0 MHz. The maximum p-p output swing is typically
1.0 volt less than V
<10
1.5 mA). Input bias current at MCI is typically 40 nA
out of the pin.
reduce the gain of the amplifier to = -39 dB (will RMI
= 5.1 K ) by shorting the output to the inverting
input (see Figure 5). The mute input has a threshold
of 1.5 volt, and the voltage at this pin must be kept
withing t h e range of ground and V
function is not used, the pin should be grounded.
Figure 4. CT Attenuator Control Block Circuit
The microphone amplifier (Pin 10, 11) has the
The muting function (Pin 12), when activated, will
Figure 5. Microphone Amplifier and MUTE
until curent limiting is reached (typically
CC
with an output impedance of
CC
. If the mute
B
, while
HYBRID AMPLIFIERS
HTI), in conjunction with an external transformer,
provide the two-to-four wire converter for interfacing
to the telephone line. The gain of the first amplifier
(HTI to HTO-) is set by external resistors (gain = -
R
amplifier, the gain of which is internally set at -1.0.
Unlike most op-amps, the amplifiers have an all-NPN
output stage, which maximizes phase margin and
gain-bandwidth. This feature ensures stability at
gains less than unity, as well as with a wide range of
reactive loads. The open loop gain of the first
amplifier is typically 80 dB, and the gain bandwidth of
each amplifier is 1.0 MHz. The maximum p-p output
swing of each amplifier is typically 1.2 volts less than
V
limiting is reached (typically 8.0 mA). The output
current capability is guaranteed to be a minimum of
5.0 mA. The bias current at HTI is typically 30 nA out
of the pin.
shown in the Expanded Logic Diagram (Figure 8). The
block labeled Zbal is the balancing network necessary
to match the line impedance.
FILTER
the external components. The circuit within the
IL34118, from pins FI to FO is a buffer with a high
input impedance (>1.0 M ), and a low output
impedance (<50
components determines whether the circuit is a high-
pass filter (as shown in Figure 8), a low-pass filter, or
a band-pass filter.
As a high pass filter, with the components shown in
Figure 6 the filter will keep out 60 Hz (and 120 Hz) hum
which can be picked up by the external telephone
lines.
HF
CC
/R
The two hybrid amplifiers (at HTO+, HTO-, and
The connections to the coupling transformer are
The operation of the filter circuit is determined by
with an output impedance of <10
HI
in Figure 8), and its output drives the second
Figure 6. High Pass Filter
). The configuration of the external
SLS
System Logic
Semiconductor
until current