SC16C850IBS NXP [NXP Semiconductors], SC16C850IBS Datasheet - Page 25

• Manufacturer Part Number: SC16C850IBS
• Description: 2.5 V to 3.3 V UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and 16 mode or 68 mode parallel bus interface
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
SC16C850_1
Product data sheet
7.3.1 FIFO mode
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, and set the receive FIFO
trigger levels.
Table 10.
[1]
[2]
Table 11.
[1]
Bit
7:6
5:4
3
2
1
0
FCR[7]
0
0
1
1
For 128-byte FIFO mode, refer to
For 128-byte FIFO mode, refer to
When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and
transmit trigger levels are set by RXINTLVL, TXINTLVL registers (see
Symbol
FCR[7:6] Receive trigger level in 32-byte FIFO mode
FCR[5:4] Transmit trigger level in 32-byte FIFO mode
FCR[3]
FCR[2]
FCR[1]
FCR[0]
FIFO Control Register bits description
RCVR trigger levels
FCR[6]
0
1
0
1
Description
These bits are used to set the trigger levels for receive FIFO interrupt and flow
control. The SC16C850 will issue a receive ready interrupt when the number of
characters in the receive FIFO reaches the selected trigger level. Refer to
Table
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C850 will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
Table
reserved
XMIT FIFO reset.
RCVR FIFO reset.
FIFO enable.
2.5 V to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO counter
logic. This bit will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
Rev. 01 — 10 January 2008
11.
12.
RX FIFO trigger level (bytes) in 32-byte FIFO mode
8
16
24
28
Section
Section
7.16,
7.15,
Section
Section
7.17,
7.17,
Section
Section
[1]
[2]
.
.
7.18.
7.18.
Section 6.4 “FIFO
SC16C850
© NXP B.V. 2008. All rights reserved.
operation”).
[1]
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