LTC2629 LINER [Linear Technology], LTC2629 Datasheet - Page 15

• Manufacturer Part Number: LTC2629
• Description: Quad 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface
• Manufacturer: LINER [Linear Technology]

OPERATIO
Table 2
COMMAND*
ADDRESS (n)*
*Command and address codes not shown are reserved and should not be used.
C3 C2 C1 C0
A3 A2 A1 A0
loads a 16-bit data word from the 32-bit shift register into
the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path and
registers are shown in the Block Diagram.
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
0
1
1
0
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
1
U
Write to Input Register n
Update (Power Up) DAC Register n
Write to Input Register n, Update (Power Up) All n
Write to and Update (Power Up) n
Power Down n
No Operation
DAC A
DAC B
DAC C
DAC D
All DACs
Write Word Protocol for LTC2609/LTC2619/LTC1629
Input Word (LTC2609)
Input Word (LTC2619)
Input Word (LTC2629)
C3
C3
C3
S
C2
C2
C2
SLAVE ADDRESS
C1 C0
C1 C0
C1 C0
1ST DATA BYTE
1ST DATA BYTE
1ST DATA BYTE
A3
A3
A3
A2
A2
A2
W
A1
A1
A1
A
1ST DATA BYTE
A0
A0
A0
D15
D13
D11
D14
D12
D10
D13
D11
D9
A
2ND DATA BYTE
2ND DATA BYTE
2ND DATA BYTE
Figure 3
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
D10 D9 D8
2ND DATA BYTE
D8
INPUT WORD
D7 D6
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than four outputs are needed. When in power-down, the
buffer amplifiers, bias circuits and reference inputs are
disabled, and draw essentially zero current. The DAC
outputs are put into a high impedance state, and the
output pins are passively pulled to REFLO through
individual 90k resistors. Input- and DAC-register contents
are not disturbed during power down.
Any channel or combination of channels can be put into
power-down mode by using command 0100b in
combination with the appropriate DAC address, (n). The
16-bit data word is ignored. The supply current is reduced
by approximately 1/4 for each DAC powered down.
The effective resistance at REFx (Pins 3, 6, 12 and 15)
are at high impedance (typically > 1GΩ) when the corre-
sponding DACs are powered down. Normal operation can
be resumed by executing any command which includes a
DAC update, as shown in Table 2.
The selected DAC is powered up as its voltage output is
updated. When a DAC which is in a powered-down state
is powered up and updated, normal settling is delayed. If
less than four DACs are in a powered-down state prior to
the update command, the power-up delay time is 5µs.
If on the other hand, all four DACs are powered down,
D7 D6 D5 D4 D3 D2 D1 D0
D5 D4 D3 D2 D1 D0
LTC2609/LTC2619/LTC2629
A
3RD DATA BYTE
3RD DATA BYTE
3RD DATA BYTE
3RD DATA BYTE
A
P
X
X
D1 D0
X
X
2609
X
X
F03
15
26091929f