LTC2629 LINER [Linear Technology], LTC2629 Datasheet - Page 13

• Manufacturer Part Number: LTC2629
• Description: Quad 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface
• Manufacturer: LINER [Linear Technology]

OPERATIO
Power-On Reset
The LTC2609/LTC2619/LTC2629 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2609-1/
LTC2619-1/LTC2629-1 set the voltage outputs to midscale
when power is first applied.
For some applications, downstream circuits are active
during DAC power-up and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2609/
LTC2619/LTC2629 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REFx (Pins 3, 6, 12 and 15) should be kept
within the range – 0.3V ≤ REFx ≤ V
Maximum Ratings). Particular care should be taken to
observe these limits during power supply turn-on and
turn-off sequences, when the voltage at V
transition. The REFx pins can be clamped to stay below the
maximum voltage by using Schottky diodes as shown in
Figure 2, thereby easing sequencing constraints.
Transfer Function
The digital-to-analog transfer function is:
Figure 2. Use of Schottky Diodes for Power Supply Sequencing
V
OUT IDEAL
(
)
=
LTC2609/
LTC2619/
LTC2629
⎛
⎜
⎝
U
2
k
N
REFA
REFB
REFC
REFD
⎞
⎟
⎠
V
CC
[
REFx REFLO
16
3
6
12
15
2609 F02
–
V
CC
CC
+ 0.3V (see Absolute
]
+
CC
REFD
REFA
REFB
REFC
REFLO
(Pin 16) is in
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and REFx is the voltage at REFA,
REFB, REFC and REFD (Pins 3, 6, 12 and 15).
Serial Digital Interface
The LTC2609/LTC2619/LTC2629 communicate with a host
using the standard 2-wire I
gram (Figure 1) shows the timing relationship of the sig-
nals on the bus. The two bus lines, SDA and SCL, must be
high when the bus is not in use. External pull-up resistors
or current sources are required on these lines. The value
of these pull-up resistors is dependent on the power sup-
ply and can be obtained from the I
I
be necessary if the bus capacitance is greater than 200pF.
The LTC2609/LTC2619/LTC2629 are receive-only (slave)
devices. The master can write to the LTC2609/LTC2619/
LTC2629. The LTC2609/LTC2619/LTC2629 do not re-
spond to a read from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition.
A START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while SCL
is high. The bus is then free for communication with
another I
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the latest
byte of information was received. The Acknowledge re-
lated clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge
clock pulse. The slave-receiver must pull down the SDA
bus line during the Acknowledge clock pulse so that it
2
C bus operating in the fast mode, an active pull-up will
LTC2609/LTC2619/LTC2629
2
C device.
2
C interface. The Timing Dia-
2
C specifications. For an
13
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