LTC2626 LINER [Linear Technology], LTC2626 Datasheet - Page 14

• Manufacturer Part Number: LTC2626
• Description: 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface
• Manufacturer: LINER [Linear Technology]

LTC2606/LTC2616/LTC2626
OPERATIO
Table 1. Slave Address Map
In addition to the address selected by the address pins, the
parts also respond to a global address. This address
allows a common write to all LTC2606, LTC2616 and
LTC2626 parts to be accomplished with one 3-byte write
transaction on the I
on-chip hardwired address and is not selectable by CA0,
CA1 and CA2.
The addresses corresponding to the states of CA0, CA1
and CA2 and the global address are shown in Table 1. The
maximum capacitive load allowed on the address pins
(CA0, CA1 and CA2) is 10pF, as these pins are driven
during address detection to determine if they are floating.
14
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
GND
GND
GND
GND
GND
GND
GND
GND
CA2
GND
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
GLOBAL ADDRESS
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
GND
GND
GND
GND
GND
GND
GND
GND
GND
CA1
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
U
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
FLOAT
GND
GND
GND
GND
GND
GND
GND
GND
GND
CA0
V
V
V
V
V
V
V
V
V
2
CC
CC
CC
CC
CC
CC
CC
CC
CC
C bus. The global address is a 7-bit
A6
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A5
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A4
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Write Word Protocol
The master initiates communication with the LTC2606/
LTC2616/LTC2626 with a START condition and a 7-bit slave
address followed by the Write bit (W) = 0. The LTC2606/
LTC2616/LTC2626 acknowledges by pulling the SDA pin
low at the 9th clock if the 7-bit slave address matches the
address of the parts (set by CA0, CA1 and CA2) or the global
address. The master then transmits three bytes of data. The
LTC2606/LTC2616/LTC2626 acknowledges each byte of
data by pulling the SDA line low at the 9th clock of each data
byte transmission. After receiving three complete bytes of
data, the LTC2606/LTC2616/LTC2626 executes the com-
mand specified in the 24-bit input word.
If more than three data bytes are transmitted after a valid
7-bit slave address, the LTC2606/LTC2616/LTC2626 do
not acknowledge the extra bytes of data (SDA is high
during the 9th clock).
The format of the three data bytes is shown in Figure 3. The
first byte of the input word consists of the 4-bit command
and four don’t care bits. The next two bytes consist of the
16-bit data word. The 16-bit data word consists of the
16-, 14- or 12-bit input code, MSB to LSB, followed by 0,
2 or 4 don’t care bits (LTC2606, LTC2616 and LTC2626
respectively). A typical LTC2606 write transaction is shown
in Figure 4.
The command assignments (C3-C0) are shown in Table 2.
The first four commands in the table consist of write and
update operations. A write operation loads a 16-bit data
word from the 32-bit shift register into the input register.
In an update operation, the data word is copied from the
input register to the DAC register and converted to an ana-
log voltage at the DAC output. The update operation also
powers up the DAC if it had been in power-down mode. The
data path and registers are shown in the Block Diagram.
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever the DAC
output is not needed. When in power-down, the buffer
amplifier, bias circuit and reference input is disabled and
draws essentially zero current. The DAC output is put into
26061626f