LTC2355-12_09 LINER [Linear Technology], LTC2355-12_09 Datasheet - Page 13

• Manufacturer Part Number: LTC2355-12_09
• Description: Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown
• Manufacturer: LINER [Linear Technology]

applications inFormation
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC2355-12/LTC2355-14, a printed
circuit board with ground plane is required. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track. If optimum phase match
between the inputs is desired, the length of the two input
wires should be kept matched.
High quality tantalum and ceramic bypass capacitors
should be used at the V
Block Diagram on the first page of this data sheet. For
optimum performance, a 10µF surface mount Tantalum
capacitor with a 0.1µF ceramic is recommended for the
V
DD
and V
OPTIONAL INPUT FILTERING
REF
pins. Alternatively, 10µF ceramic chip capaci-
Figure 5. Recommended Layout
V
REF
DD
BYPASS 0805 SIZE
and V
V
DD
REF
BYPASS 0805 SIZE
pins as shown in the
tors such as Murata GRM235Y5V106Z016 may be used.
The capacitors must be located as close to the pins as
possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as
wide as possible.
Figure 5 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated
at the LTC2355-12/LTC2355-14 GND (Pins 4, 5, 6 and
exposed pad). The ground return from the LTC2355-
12/LTC2355-14 (Pins 4, 5, 6 and exposed pad) to the
power supply should be low impedance for noise free
operation. In applications where the ADC data outputs
and control signals are connected to a continuously ac-
tive microprocessor bus, it is possible to get errors in the
conversion results. These errors are due to feedthrough
from the microprocessor to the successive approximation
comparator. The problem can be eliminated by forcing the
microprocessor into a Wait state during conversion or by
using three-state buffers to isolate the ADC data bus.
POWER-DOWN MODES
Upon power-up, the LTC2355-12/LTC2355-14 is initial-
ized to the active state and is ready for conversion.
The Nap and Sleep mode waveforms show the power-
down modes for the LTC2355-12/LTC2355-14. The SCK
and CONV inputs control the power-down modes (see
Timing Diagrams). Two rising edges at CONV, without
any intervening rising edges at SCK, put the LTC2355-
12/LTC2355-14 in Nap mode and the power consumption
drops from 18mW to 4mW. The internal reference remains
powered in Nap mode. One or more rising edges at SCK
wake up the LTC2355-12/LTC2355-14 very quickly, and
CONV can start an accurate conversion within a clock
cycle. Four rising edges at CONV, without any interven-
ing rising edges at SCK, put the LTC2355-12/LTC2355-14
LTC2355-12/LTC2355-14

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