LTC2207 LINER [Linear Technology], LTC2207 Datasheet - Page 22

• Manufacturer Part Number: LTC2207
• Description: 16-Bit, 105Msps/80Msps ADCs
• Manufacturer: LINER [Linear Technology]

LTC2207/LTC2206
APPLICATIONS INFORMATION
Driving the Encode Inputs
The noise performance of the LTC2207/LTC2206 can
depend on the encode signal quality as much as for the
analog input. The encode inputs are intended to be driven
differentially, primarily for noise immunity from common
mode noise sources. Each input is biased through a 6k
resistor to a 1.6V bias. The bias resistors set the DC oper-
ating point for transformer coupled drive circuits and can
set the logic threshold for single-ended drive circuits.
Any noise present on the encode signal will result in ad-
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using trans-
3. If the ADC is clocked with a fi xed frequency sinusoidal
4. Balance the capacitance and series resistance at both
The encode inputs have a common mode range of 1.2V
to V
single-ended drive.
22
former coupling, use a higher turns ratio to increase the
amplitude.
signal, fi lter the encode signal to reduce wideband
noise.
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
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. Each input may be driven from ground to V
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for
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2207 is 105Msps.
The maximum encode rate for the LTC2206 is 80Msps. For
the ADC to operate properly the encode signal should have
a 50% (±5%) duty cycle. Each half cycle must be at least
4.52ns for the LTC2207 internal circuitry to have enough
settling time for proper operation. For the LTC2206, each
half cycle must be at least 5.94ns. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using
a transformer or using symmetric differential logic such
as PECL or LVDS. When using a single-ended ENCODE
signal asymmetric rise and fall times can result in duty
cycles that are far from 50%.
An optional clock duty cycle stabilizer can be used if the
input clock does not have a 50% duty cycle. This circuit
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 30% to 70% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin must be
connected to 1/3V
The lower limit of the LTC2207/LTC2206 sample rate is
determined by droop of the sample and hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specifi ed minimum operating
frequency for the LTC2207/LTC2206 is 1Msps.
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or 2/3V
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using external resistors.
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