LTC1865 LINER [Linear Technology], LTC1865 Datasheet - Page 7

• Manufacturer Part Number: LTC1865
• Description: Ultra-Tiny, Differential, 16-Bit ADC with SPI Interface SPI Interface
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
started, this operation can not be aborted except by a low
power supply condition (V
internal power-on reset signal.
After the completion of a conversion, the LTC2452 enters
the SLEEP state and remains there until both the chip
select and serial clock inputs are low (CS = SCK = LOW).
Following this condition, the ADC transitions into the DATA
OUTPUT state.
While in the SLEEP state, whenever the chip select input
is pulled high (CS = HIGH), the LTC2452’s power supply
current is reduced to less than 200nA. When the chip select
input is pulled low (CS = LOW), and SCK is maintained
at a HIGH logic level, the LTC2452 will return to a normal
power consumption level. During the SLEEP state, the
result of the last conversion is held indefinitely in a static
register.
Upon entering the DATA OUTPUT state, SDO outputs the
sign (D15) of the conversion result. During this state,
the ADC shifts the conversion result serially through the
SDO output pin under the control of the SCK input pin.
There is no latency in generating this data and the result
Figure 2. LTC2452 State Transition Diagram
NO
NO
POWER-ON RESET
DATA OUTPUT
16TH FALLING
EDGE OF SCK
SCK = LOW
CS = LOW?
CS = HIGH?
CONVERT
CC
SLEEP
AND
OR
< 2.1V) which generates an
YES
YES
2452 F02
corresponds to the last completed conversion. A new bit
of data appears at the SDO pin following each falling edge
detected at the SCK input pin and appears from MSB to
LSB. The user can reliably latch this data on every rising
edge of the external serial clock signal driving the SCK
pin (see Figure 3).
The DATA OUTPUT state concludes in one of two different
ways. First, the DATA OUTPUT state operation is completed
once all 16 data bits have been shifted out and the clock
then goes low. This corresponds to the 16
of SCK. Second, the DATA OUTPUT state can be aborted
at any time by a LOW-to-HIGH transition on the CS input.
Following either one of these two actions, the LTC2452
will enter the CONVERT state and initiate a new conver-
sion cycle.
Power-Up Sequence
When the power supply voltage (V
verter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
When V
generates an internal power-on reset (POR) signal for
approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2452 starts a
conversion cycle and follows the succession of states shown
in Figure 2. The first conversion result following POR is
accurate within the specifications of the device if the power
supply voltage V
(2.7V to 5.5V) before the end of the POR time interval.
Ease of Use
The LTC2452 data output has no latency, filter settling delay
or redundant results associated with the conversion cycle.
There is a one-to-one correspondence between the conver-
sion and the output data. Therefore, multiplexing multiple
analog input voltages requires no special actions.
The LTC2452 performs offset calibrations every conver-
sion. This calibration is transparent to the user and has no
effect upon the cyclic operation described previously. The
advantage of continuous calibration is stability of the ADC
performance with respect to time and temperature.
CC
rises above this critical threshold, the converter
CC
is restored within the operating range
CC
) applied to the con-
LTC2452
th
falling edge
2452fc
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