LTC1865 LINER [Linear Technology], LTC1865 Datasheet - Page 10

• Manufacturer Part Number: LTC1865
• Description: Ultra-Tiny, Differential, 16-Bit ADC with SPI Interface SPI Interface
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
LTC2452
Serial Interface Operation Modes
The modes of operation can be summarized as follows:
1) The LTC2452 functions with SCK idle high (commonly
2) After the 16th bit is read, the user can choose one of
3) At any time during the Data Output state, pulling CS
4) When SCK = HIGH, it is possible to monitor the conver-
10
known as CPOL = 1) or idle low (commonly known as
CPOL = 0).
two ways to begin a new conversion. First, one can
pull CS high (CS = ↑). Second, one can use a high-low
transition on SCK (SCK = ↓).
high (CS = ↑) causes the part to leave the I/O state,
abort the output and begin a new conversion.
sion status by pulling CS low and watching for SDO to
go low. This feature is available only in the idle-high
(CPOL = 1) mode.
CS
SD0
SCK
CS
SD0
SCK
CONVERT
CONVERT
Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example.
The Rising Edge of CS Starts a New Conversion
Figure 7. Idle-High (CPOL = 1) Clock Operation Example.
A 17th Clock Pulse is Used to Trigger a New Conversion Cycle
SLEEP
SLEEP
clk
clk
D
1
1
D
15
15
clk
clk
2
D
2
D
14
14
clk
Serial Clock Idle-High (CPOL = 1) Examples
In Figure 6, following a conversion cycle the LTC2452
automatically enters the low power sleep mode. The user
can monitor the conversion status at convenient intervals
using CS and SDO.
Pulling CS LOW while SCK is HIGH tests whether or not
the chip is in the CONVERT state. While in the CONVERT
state, SDO is HIGH while CS is LOW. In the SLEEP state,
SDO is LOW while CS is LOW. These tests are not required
operational steps but may be useful for some applications.
When the data is available, the user applies 16 clock cycles
to transfer the result. The CS rising edge is then used to
initiate a new conversion.
The operation example of Figure 7 is identical to that of
Figure 6, except the new conversion cycle is triggered by
the falling edge of the serial clock (SCK). A 17th clock
pulse is used to trigger a new conversion cycle.
clk
3
D
3
D
13
13
DATA OUTPUT
clk
DATA OUTPUT
clk
D
4
D
4
12
12
D
D
2
clk
2
clk
15
15
D
D
1
1
clk
clk
16
D
16
D
0
0
clk
17
CONVERT
CONVERT
2452 F06
2452 F07
2452fc