AD5243 AD [Analog Devices], AD5243 Datasheet - Page 5

• Manufacturer Part Number: AD5243
• Description: Dual 256-Position I2C Compatible Digital Potentiometer
• Manufacturer: AD [Analog Devices]

TIMING CHARACTERISTICS—ALL VERSIONS
V
Table 3.
Parameter
I
NOTES
1
2
3
4
5
6
7
8
9
10
11
See notes at end of section.
2
P
All dynamic characteristics use V
Guaranteed by design and not subject to production test.
Typical specifications represent average readings at 25°C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
V
INL and DNL are measured at V
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
See timing diagrams for locations of measured values.
The maximum t
C INTERFACE TIMING CHARACTERISTICS
DISS
DD
AB
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
F
R
SU;STO
= V
is calculated from (I
= 5V ± 10%, or 3V ± 10%; V
Fall Time of Both SDA and SCL Signals
Rise Time of Both SDA and SCL Signals
Bus Free Time between STOP and START
Low Period of SCL Clock
DD
High Period of SCL Clock
Setup Time for Repeated START Condition
Setup Time for STOP Condition
Hold Time (Repeated START)
Data Setup Time
, wiper (VW) = no connect.
Data Hold Time
HD:DAT
must be met only if the device does not stretch the low period (t
DD
× V
11
DD
W
). CMOS logic level inputs result in minimum power dissipation.
DD
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
= 5 V.
A
= V
DD
; V
10
(Specifications Apply to All Parts)
B
= 0 V; −40°C < T
DD
Symbol
f
t
t
t
t
t
t
t
t
t
t
SCL
1
2
3
4
5
6
7
8
9
10
= 5 V.
Rev. 0 | Page 5 of 20
A
< +125°C; unless otherwise noted.
Conditions
After this period, the first clock pulse is
generated.
LOW
) of the SCL signal.
A
Min
0
1.3
0.6
1.3
0.6
0.6
100
0.6
= V
DD
AD5243/AD5248
and V
Typ
B
= 0 V.
1
Max
400
0.9
300
300
Unit
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs