AD5243 AD [Analog Devices], AD5243 Datasheet - Page 14

• Manufacturer Part Number: AD5243
• Description: Dual 256-Position I2C Compatible Digital Potentiometer
• Manufacturer: AD [Analog Devices]

AD5243/AD5248
Typical device-to-device matching is process lot dependent and
may vary by up to ±30%. Because the resistance element is
processed in thin film technology, the change in R
temperature has a very low 35 ppm/°C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of V
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the volt-
age applied across terminal AB divided by the 256 positions of
the potentiometer divider. The general equation defining the
output voltage at V
voltage applied to terminals A and B is
A more accurate calculation, which includes the effect of wiper
resistance, V
Operation of the digital potentiometer in the divider mode
results in a more accurate operation overtemperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, shown in Figure 39 and
Figure 40. This applies to the digital input pins SDA, SCL, AD0,
and AD1 (AD5248 only).
V
V
W
W
(
(
D
D
)
)
W
=
=
Figure 38. Potentiometer Mode Configuration
, is
256
R
D
WB
R
AB
V
W
(
D
A
with respect to ground for any valid input
V
)
I
+
V
256
A
+
256
A
B
−
R
WA
D
R
DD
W
AB
V
(
D
to GND, which must be
B
WA
)
V
and R
V
B
O
WB
and not the
AB
with
(3)
(4)
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TERMINAL VOLTAGE OPERATING RANGE
The AD5243/AD5248 V
boundary conditions for proper 3-terminal digital potentiome-
ter operation. Supply signals present on Terminals A, B, and W
that exceed V
biased diodes (see Figure 41).
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminals A, B, and W (see Figure 41), it is important to
power V
and W; otherwise, the diode is forward biased such that V
powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, V
order of powering V
important as long as they are powered after V
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with disk or chip ceramic capacitors
of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum or electro-
lytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 42). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
Figure 41. Maximum Terminal Voltages Set by V
DD
DD
, digital inputs, and then V
/GND before applying any voltage to Terminals A, B,
Figure 40. ESD Protection of Resistor Terminals
DD
Figure 39. ESD Protection of Digital Pins
or GND are clamped by the internal forward
A
, V
A, B, W
GND
GND
B
DD
, V
340Ω
and GND power supply defines the
W
, and the digital inputs is not
LOGIC
A
, V
B
V
A
W
B
GND
, and V
DD
DD
DD
/GND.
W
and GND
. The relative
DD
is