MC2GH256NMCA-2SA00 SAMSUNG [Samsung semiconductor], MC2GH256NMCA-2SA00 Datasheet - Page 72

• Manufacturer Part Number: MC2GH256NMCA-2SA00
• Description: SAMSUNG MultiMediaCard
• Manufacturer: SAMSUNG [Samsung semiconductor]

All timing diagrams use the following schematics and abbreviations:
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card respectively host output
driver, while Z-bit is driven to (respectively kept) HIGH by the pull-up resistors R
bits are less sensitive to noise.
All timing values are defined in Table 6-25.
6.12.1 Command and Response
Both host command and card response are clocked out with the rising edge of the host clock.
• Card identification and card operation conditions timing
The card identification (CMD2) and card operation conditions (CMD1) timing are processed in the open-drain mode. The
card response to the host command starts after exactly N
CMD
• Assign a card relative address
The SET_RCA (CMD 3) is also processed in the open-drain mode. The minimum delay between the host command and
card response is N
CMD
6.12 Timing Diagrams
Revision 0.3
Symbol
CRC
D
S
T
P
E
Z
X
*
←⎯⎯ Host Command ⎯⎯→ ← N
←⎯⎯ Host Command ⎯⎯→ ←⎯N
S T
S T
CR
clock cycles.
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Start bit (= ‘0’)
Transmitter bit (Host = ‘1’, Card = ‘0’)
One-cycle pull-up (= ‘1’)
End bit (=’1’)
High impedance state (-> = ‘1’)
Driven value, ‘1’ or ‘0’
Data bits
Repetition
Cyclic redundancy check bits (7 bits)
Card active
Host active
Figure 6-7 : Identification Timing (Card Identification Mode)
Figure 6-8 : SET_RCA Timing (Card Identification Mode)
CRC E Z
CRC E Z
Table 6-24 : Timing Diagram Symbols
ID
CR
* * *
* * *
cycles ⎯→
cycles ⎯→ ←⎯⎯ Response ⎯⎯⎯→
ID
Z S T
Z S T
72
clock cycles.
←⎯ CID or OCR ⎯⎯→
Definition
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CMD
CRC E Z Z Z
respectively R
Z Z Z
MultiMediaCard
DAT
. Actively-driven P-
Sep.22.2005
TM