ST6285 STMICROELECTRONICS [STMicroelectronics], ST6285 Datasheet
ST6285
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ST6285 Summary of contents
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... On-chip Clock oscillator can be driven by Quartz Crystal or Ceramic resonator One external Non-Maskable Interrupt ST6285-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port). August 1999 ST62T85B/E85B EEPROM AND A/D CONVERTER with ...
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ST62T85B/E85B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 ...
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ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.2 PACKAGE THERMAL CHARACTERISTIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.3 .ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ST6285B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.2 ROM READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 1.3 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.3.1 Transfer of Customer Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 1.3.2 Listing Generation and Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4/76 4 Table of Contents Document Page 76 ...
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... EPROM/OTP versions only) PP mon core is surrounded by a number of on-chip peripherals. The ST62E85B is the erasable EPROM version of the ST62T85B device, which may be used to em- ulate the ST62T85B device, as well as the respec- tive ST6285B ROM devices. PORT A 8-BIT PORT B ARTIMER UART PORT C LCD DRIVER ...
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ST62T85B/E85B INTRODUCTION (Cont’d) OTP and EPROM devices are functionally identi- cal. The ROM based versions offer the same func- tionality selecting as ROM options the options de- fined in the programmable option byte of the OTP/EPROM versions.OTP devices offer all ...
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... Figure 2. ST6285B Pin Description S41 2 S42 3 S43 4 S44 5 S45 6 S46 7 S47 8 S48 9 S49 10 S50 11 S51 12 S52 13 S53 14 S54 15 S55 16 S56 17 PB3 18 PB2 19 PB1 20 PB0 21 TEST OSCout 23 OSCin 24 RESET ...
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ST62T85B/E85B 1.2 PIN DESCRIPTIONS V and V . Power is supplied to the MCU via DD SS these two pins the power connection and the ground connection. SS OSCin and OSCout. These pins are internally ...
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MEMORY MAP 1.3.1 Introduction The MCU operates in three separate memory spaces: Program space, Data space, and Stack space. Operation in these three memory spaces is described in the following paragraphs. Briefly, Program space contains user program code in ...
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ST62T85B/E85B MEMORY MAP (Cont’d) Table 1. ST62E85B/T80B Program Memory Map ROM Page Device Address Description 0000h-007Fh Page 0 0080h-07FFh User ROM 0800h-0F9Fh User ROM 0FA0h-0FEFh Page 1 0FF0h-0FF7h Interrupt Vectors “STATIC” 0FF8h-0FFBh 0FFCh-0FFDh NMI Vector 0FFEh-0FFFh Reset Vector 0000h-000Fh Page ...
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MEMORY MAP (Cont’d) 1.3.3 Data Space Data Space accommodates all the data necessary for processing the user program. This space com- prises the RAM resource, the processor core and peripheral registers, as well as read-only data such as constants and ...
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ST62T85B/E85B MEMORY MAP (Cont’d) 1.3.5 Data Window Register (DWR) The Data read-only memory window is located from address 0040h to address 007Fh in Data space. It allows direct reading of 64 consecutive bytes locat- ed anywhere in program memory, between ...
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MEMORY MAP (Cont’d) 1.3.6 Data RAM/EEPROM and LCD RAM Bank Register (DRBR) Address: CBh — Write only 7 - DRBR6 DRBR5 DRBR4 DRBR3 - Bit 7 = This bit is not used Bit 6 - DRBR6. This bit, when set, ...
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ST62T85B/E85B MEMORY MAP (Cont’d) 1.3.7 EEPROM Description EEPROM memory is located in 64-byte pages in data space. This memory may be used by the user program for non-volatile data storage. Data space from 00h to 3Fh is paged as described ...
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MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in write mode, ...
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ST62T85B/E85B 1.4 PROGRAMMING MODES 1.4.1 Option Byte The Option Byte allows configuration capability to the MCUs. Option byte’s content is automatically read, and the selected options enabled, when the chip reset is activated. It can only be accessed during the ...
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CENTRAL PROCESSING UNIT 2.1 INTRODUCTION The CPU Core of ST6 devices is independent of the I/O or Memory configuration. As such, it may be thought independent central processor communicating with on-chip I/O, Memory and Pe- ripherals ...
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ST62T85B/E85B CPU REGISTERS (Cont’d) However, if the program space contains more than 4096 bytes, the additional memory in program space can be addressed by using the Program Bank Switch register. The PC value is incremented after reading the ad- dress ...
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CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM 3.1.1 Main Oscillator The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a ...
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ST62T85B/E85B 3.2 RESETS The MCU can be reset in three ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may be ...
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RESETS (Cont’d) 3.2.3 Watchdog Reset The MCU provides a Watchdog timer function in order to ensure graceful recovery from software upsets. If the Watchdog register is not refreshed before an end-of-count condition is reached, the internal reset will be activated. ...
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ST62T85B/E85B RESETS (Cont’d) Table 7. Register Reset Status Register EEPROM Control Register Port Data Registers Port A,B Direction Register Port A,B Option Register Interrupt Option Register SPI Registers LCD Mode Control Register UART Control UART Data Register ...
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DIGITAL WATCHDOG The digital Watchdog consists of a reloadable downcounter timer which can be used to provide controlled recovery from software upsets. The Watchdog circuit generates a Reset when the downcounter reaches zero. User software can prevent this reset ...
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ST62T85B/E85B DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register (DWDR). This register is set to 0FEh on ...
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DIGITAL WATCHDOG (Cont’d) 3.3.1 Digital Watchdog Register (DWDR) Address: 0D8h — Read/Write Reset status: 1111 1110b Bit Watchdog Control bit If the hardware option is selected, this bit is forced ...
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ST62T85B/E85B DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of 28 ...
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INTERRUPTS The CPU can manage four Maskable Interrupt sources, in addition to a Non Maskable Interrupt source (top priority interrupt). Each source is asso- ciated with a specific Interrupt Vector which con- tains a Jump instruction to the associated ...
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ST62T85B/E85B INTERRUPTS (Cont’d) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call pro- cedure, indeed the user can consider the interrupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the ...
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INTERRUPTS (Cont’d) 3.4.3 Interrupt Option Register (IOR) The Interrupt Option Register (IOR) is used to en- able/disable the individual interrupt sources and to select the operating mode of the external interrupt inputs. This register is write-only and cannot be accessed ...
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ST62T85B/E85B INTERRUPTS (Cont’d) Figure 16. Interrupt Block Diagram NMI SPI FROM REGISTER PORT A,B,C SINGLE BIT ENABLE PBE V DD PORT A PBE PORT B PORT C PBE Bits TIMER1 ARTIMER A/D CONVERTER RXRDY RXIEN TXMT TXIEN 30/ ...
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POWER SAVING MODES The WAIT and STOP modes have been imple- mented in the ST62xx family of MCUs in order to reduce the product’s electrical consumption during idle periods. These two power saving modes are described in the following ...
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ST62T85B/E85B POWER SAVING MODE (Cont’d) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be noted that the restart ...
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ON-CHIP PERIPHERALS 4.1 I/O PORTS The MCU features Input/Output lines which may be individually programmed as any of the following input or output configurations: – Input without pull-up or interrupt – Input with pull-up and interrupt – Input with ...
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ST62T85B/E85B I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option reg- isters (OR). ...
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I/O PORTS (Cont’d) 4.1.2 Safe I/O State Switching Sequence Switching the I/O ports from one state to another should be done in a sequence which ensures that no unwanted side effects can occur. The recom- mended safe transitions are illustrated ...
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ST62T85B/E85B I/O PORTS (Cont’d) Table 13. I/O Port configuration for the ST62T85B/E85B MODE AVAILABLE ON PA4-PA7 Input PB0-PB3 PC4-PC7 Input PA4-PA7 with pull up PB0-PB3 (Reset state) PC4-PC7 Input PA4-PA7 with pull up PB0-PB3 with interrupt PC4-PC7 PB0-PB3 Analog Input ...
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I/O PORTS (Cont’d) 4.1.3 SPI alternate functions PA6/Sin and PA5/Scl pins must be configured as input through the DDR and OR registers to be used as data in and data clock (Slave mode) for the SPI. All input modes are ...
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ST62T85B/E85B Figure 19. Peripheral Interface Configuration of Serial I/O TImer 1, ARTimer V DD PB0/RXD1 PB1/TXD1 V DD PA7/Sout PA6/Sin PA5/SCL PA4/TIM1 38/76 38 PID RXD DR UART IARTOE PID DR 0 MUX 1 TXD PP/OD OPR OUT 0 MUX ...
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I/O PORTS (Cont’d) 4.1.5 I/O Port Option Registers ORA/B/C (CCh PA, CEh PB, CFh PC) Read/Write 7 Px7 Px6 Px5 Px4 Px3 Px2 Bit 7-0 = Px7 - Px0: Port Option Register bits. 4.1.6 I/O Port Data ...
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ST62T85B/E85B 4.2 TIMER The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 The peripheral may be configured in three different operating modes. Figure 20 shows ...
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TIMER (Cont’d) 4.2.1 Timer Operating Modes There are three operating modes, which are se- lected by the TOUT and DOUT bits (see TSCR register). These three modes correspond to the two clocks which can be connected to the 7-bit prescaler ...
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ST62T85B/E85B TIMER (Cont’d) 4.2.3 Application Notes The user can select the presence of an on-chip pull-up on the TIMER pin as option. TMZ is set when the counter reaches zero; howev- er, it may also be set by writing 00h ...
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AUTO-RELOAD TIMER The Auto-Reload Timer (AR Timer) on-chip pe- ripheral consists of an 8-bit timer/counter with compare and capture/reload capabilities and of a 7-bit prescaler with a clock multiplexer, enabling the clock input to be selected as f Mode ...
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ST62T85B/E85B AUTO-RELOAD TIMER (Cont’d) Figure 22. AR Timer Block Diagram f INT M f 7-Bit /3 INT U AR PRESCALER X PS0-PS2 CC0-CC1 44/76 44 DATA BUS 8 AR COMPARE REGISTER 8 CPF COMPARE 8 OVF 8-Bit LOAD AR COUNTER ...
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AUTO-RELOAD TIMER (Cont’d) 4.3.3 AR Timer Registers AR Mode Control Register (ARMC) Address: E5h — Read/Write Reset status: 00h 7 TCLD TEN - - CPIE OVIE The AR Mode Control Register ARMC is used to program the different operating modes ...
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ST62T85B/E85B AUTO-RELOAD TIMER (Cont’d) AR Status Control Register 1(ARSC1) Address: E7h — Read/Write 7 PS2 PS1 PS0 Bist 7-5 = PS2-PS0: Prescaler Division Selection Bits 2-0. These bits determine the Prescaler divi- sion ratio. The prescaler itself ...
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(Universal Asynchronous Receiver/Transmitter) The UART provides the basic hardware for asyn- chronous serial communication which, combined with an appropriate software routine, gives a serial interface providing communication with common baud rates (up to 38,400 Baud ...
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ST62T85B/E85B 4.4.2 CLOCK GENERATION The UART contains a built-in divider of the MCU internal clock for most common Baud Rates as shown in Table 18. Other baud rate values can be calculated from the chosen oscillator frequency di- vided by ...
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DATA RECEPTION The UART continuously looks for a falling edge on the input pin whenever a transmission is not ac- tive. Once an edge is detected it waits 1 bit time (8 states) to accommodate the Start bit, and ...
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ST62T85B/E85B REGISTERS (Cont’d) UART Control Register (UARTCR) Address: D7h, Read/Write 7 RXRDY TXMT RXIEN TXIE N BR2 BR1 Bit 7 = RXRDY. Receiver Ready . This flag be- comes active as soon as a complete byte has been received and ...
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A/D CONVERTER (ADC) The A/D converter peripheral is an 8-bit analog to digital converter with analog inputs as alternate I/O functions (the number of which is device depend- ent), offering 8-bit resolution with a typical conver- sion time of ...
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ST62T85B/E85B A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily load- ed output signals during conversion, if high preci- sion is required. Such switching will affect the sup- ...
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SERIAL PERIPHERAL INTERFACE (SPI) The on-chip SPI is an optimized serial synchro- nous interface that supports a wide range of indus- try standard SPI specifications. The on-chip SPI is controlled by small and simple user software to perform serial ...
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ST62T85B/E85B SERIAL PERIPHERAL INTERFACE (Cont’d) After 8 clock pulses (D7..D0) the output Q4 of the 4-bit binary counter becomes low, disabling the clock from the counter and the data/shift register. Q4 enables the clock to generate an interrupt on the ...
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LCD CONTROLLER-DRIVER On-chip LCD driver includes all features required for LCD driving, including multiplexing of the com- mon plates. Multiplexing allows to increase display capability without increasing the number of seg- ment outputs. In that case, the display capability ...
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ST62T85B/E85B LCD CONTROLLER-DRIVER (Cont”d) 4.7.1 Multiplexing ratio and frame frequency setting common plates COM1..COM16 can be used for multiplexing ratio of 1/8, 1/11 and 1/16. The selection is made by the bits MUX11 and MUX16 of the ...
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... LCD CONTROLLER-DRIVER (Cont”d) Address Mapping of the Display Segments The LCD RAM is located in the ST6285B data space in two pages of 64 bytes from addresses 00h to 3Fh. The LCD forms a matrix of 48 segment lines (columns) and 8 backplane lines (rows segment lines and backplane lines ac- cording to the chosen operating mode ...
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ST62T85B/E85B LCD CONTROLLER-DRIVER (Cont”d) Addressing Mapping of the LCD RAM (Cont’d) 1/8 MUX ( 448 dots COM1 bit0 COM2 bit1 COM3 bit2 COM4 bit3 COM5 bit4 COM6 bit5 COM7 bit6 COM8 bit7 S S ...
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LCD CONTROLLER-DRIVER (Cont”d) 4.7.3 Stand by or STOP operation mode No clock from the main oscillator is available in STOP mode for the LCD controller, and the con- troller is switched off when the STOP instruction is executed. All segment ...
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ST62T85B/E85B 5 SOFTWARE 5.1 ST6 ARCHITECTURE The ST6 software has been designed to fully use the hardware in the most efficient way possible while keeping byte usage to a minimum; in short, to provide byte efficient programming capability. The ST6 ...
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INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, ...
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ST62T85B/E85B INSTRUCTION SET (Cont’d) Arithmetic and Logic. These instructions are used to perform the arithmetic calculations and logic operations. In AND, ADD, CP, SUB instruc- tions one operand is always the accumulator while the other can be either a data ...
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INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. One group either sets or ...
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ST62T85B/E85B Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6 LOW 0 1 0000 0001 0010 HI 2 JRNZ 4 CALL abc 0000 1 pcr 2 ext 1 2 ...
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Opcode Map Summary (Continued) LOW 8 9 1000 1001 1010 HI 2 JRNZ abc 0000 1 pcr 2 ext 1 2 JRNZ abc 0001 1 pcr 2 ext 1 2 ...
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ST62T85B/E85B 6 ELECTRICAL CHARACTERISTICS 6.1 ABSOLUTE MAXIMUM RATINGS This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than ...
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RECOMMENDED OPERATING CONDITIONS Symbol Parameter T Operating Temperature A V Operating Supply Voltage Oscillator Frequency OSC I Pin Injection Current (positive) INJ+ I Pin Injection Current (negative) V INJ- Notes: 1. Care must be taken in ...
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ST62T85B/E85B 6.3 DC ELECTRICAL CHARACTERISTICS (T = -40 to +85 C unless otherwise specified) A Symbol Parameter V Input Low Level Voltage IL All Input pins V Input High Level Voltage IH All Input pins (1) Hysteresis Voltage V Hys ...
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AC ELECTRICAL CHARACTERISTICS (T = -40 to +85 C unless otherwise specified) A Symbol Parameter (1) t Supply Recovery Time REC Minimum Pulse Width ( RESET pin WR NMI pin T EEPROM Write Time WEE Endurance EEPROM ...
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ST62T85B/E85B 6.6 TIMER CHARACTERISTICS (T = -40 to +85 C unless otherwise specified) A Symbol Parameter f Input Frequency on TIMER Pin Pulse Width at TIMER Pin* W Note*: When available. 6.7 SPI CHARACTERISTICS (T = -40 to ...
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GENERAL INFORMATION 7.1 PACKAGE MECHANICAL DATA Figure 33. 80-Pin Plastic Quad Flat Package Figure 34. 80-Pin Ceramic Quad Flat Package Dim Min A A1 0.25 A2 2.55 2.80 3.05 0.100 0.110 0.120 B 0.30 C 0.13 D 22.95 23.20 ...
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ST62T85B/E85B GENERAL INFORMATION (Cont’d) 7.2 PACKAGE THERMAL CHARACTERISTIC Symbol Parameter RthJA Thermal Resistance 7.3 .ORDERING INFORMATION Table 29. OTP/EPROM VERSION ORDERING INFORMATION Program Sales Type Memory (Bytes) ST62E85BG1 7948 (EPROM) ST62T85BQ6 7948 (OTP) 72/76 72 Value Test Conditions Min. Typ. ...
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... LCD driver with 40 segment outputs, 8 backplane outputs, 8 software selectable segment/backplane outputs and selectable multiplexing ratio. On-chip Clock oscillator can be driven by Quartz Crystal or Ceramic resonator One external Non-Maskable Interrupt ST6285-EMU2 Emulation and Development System (connects to an MS-DOS PC via a parallel port). DEVICE SUMMARY ROM DEVICE (Bytes) ...
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... ST6285B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6285B is mask programmed ROM version of ST62T85B OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version. Figure 1. Programming wave form 0.5s min TEST 15 14V typ ...
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... ST6285B MICROCONTROLLER OPTION LIST Customer Address Contact Phone No Reference STMicroelectronics references Device ST6285B Package Plastic Quad Flat Package (Tape & Reel) Temperature Range Special Marking Authorized characters are letters, digits, ’.’, ’-’, ’/’ and spaces only. ...
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... Sweden - Switzerland - United Kingdom - U.S.A. 76/76 76 part of the contractual agreement for the creation of the specific customer mask. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points. Table 1. ROM Memory Map for ST6285B ROM Page Device Address 0000h-007Fh Page 0 0080h-07FFh 0800h-0F9Fh 0FA0h-0FEFh ...