SM8580 Nippon_Precision_Circuits America, SM8580 Datasheet - Page 17

• Manufacturer Part Number: SM8580
• Description: Real-time Clock ic
• Manufacturer: Nippon_Precision_Circuits America

Timer counter set registers (registers 4 to 7)
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Timer interrupt function example
Example of an hourly periodic timer interrupt
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Registers 4 and 5 set an 8-bit presettable binary
down-counter value for the timer interrupt func-
tion.
The value of the count can be determined by read-
ing the values of registers 6 and 7 during the
count.
The presettable binary down-counter is updated
when the data is written to registers 4 and 5.
The timer error, when the timer starts, is an inter-
val of 0 to 1 cycles of the source clock selected
during the first timer operation. Specifically, if the
source clock is 1/60Hz (1 minute cycle) and with
TE bit = 1 write timing, the maximum error that
can occur is +60 seconds. Also, timer operations
that last less than 1 source clock cycle are not nor-
mally counted.
The timer count start timing in data write mode
occurs on the first falling edge of the source clock
after the WRN rising edge that sets the TE bit,
shown in the timing diagram below. Also, when
Bank
Bank
2
2
Timer source clock
Address
Address
4
5
6
7
4
5
8
E
WRN pin
D3 pin
Timer
Timer counter output registers
Timer counter set registers
Timer counter set registers
Timer set register
Timer control
Register
Register
Address 8
TE="1" "0"
SM8580AM
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TE
Timer start
The data written to registers 4 and 5 are stored and
are not changed until replacement data is written.
This allows these bits to function as RAM bits if the
timer interrupt mode is not used (when TIE = 0).
When TE is set to 1, periodic interrupts are not
output on TIRQN, even if registers 4 and 5 are set
to zero.
the timer is stopped by changing the setting of TE
bit from 1 to 0, the count stops after the count-
down operation a maximum of 1 clock cycle of the
selected source clock later. Specifically, if the
source clock is 1/60Hz (1 minute cycle) and with
TE bit = 0 write timing, the timer count is decre-
mented and the timing stops a maximum of 60
seconds later. At this point, there is a possibility
that the timer count has decremented to zero and
generated an interrupt. Therefore, if interrupts are
not required, the TIE interrupt enable bit should be
set to avoid unwanted interrupts from occurring.
TEST
Bit 3
Bit 3
128
128
TE
8
8
1
0
Timer stop
NIPPON PRECISION CIRCUITS INC.—17
TEMP
Bit 2
Bit 2
TE="0" "1"
64
64
4
4
1
0
1
Bit 1
Bit 1
TF
32
32
1
2
2
0
1
Bit 0
Bit 0
16
16
1
1
0
1
1
1