SN74LS161D ONSEMI [ON Semiconductor], SN74LS161D Datasheet - Page 6

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SN74LS161D

Manufacturer Part Number
SN74LS161D
Description
BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS
Manufacturer
ONSEMI [ON Semiconductor]
Datasheet
Q RESPONSE TO PE
Q RESPONSE TO SR
The positive TC pulse occurs when the outputs are in the
(Q 0 Q 1 Q 2 Q 3 ) state for the LS160 and LS162 and the
(Q 0 Q 1 Q 2 Q 3 ) state for the LS161 and LS163.
The positive TC pulse is coincident with the output state
(Q 0 Q 1 Q 2 Q 3 ) state for the LS161 and LS163 and
(Q 0 Q 1 Q 2 Q 3 ) for the LS161 and LS163.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
SR or PE
TO TERMINAL COUNT OUTPUT DELAYS
CLOCK TO TERMINAL COUNT DELAYS
SETUP TIME (t s ) AND HOLD TIME (t h )
COUNT ENABLE TRICKLE INPUT
CP
FOR PARALLEL DATA INPUTS
t s (L)
RESET
PARALLEL LOAD
(See Fig. 5)
1.3 V
1.3 V
t h (L) = 0
Figure 6
t s (H)
SN54/74LS160A SN54/74LS161A
SN54/74LS162A SN54/74LS163A
COUNT OR LOAD
The shaded areas indicate when the input is permitted to
change for predictable output performance.
COUNT MODE
(See Fig. 7)
SETUP TIME (t s ) AND HOLD TIME (t h ) FOR
COUNT ENABLE (CEP) AND (CET) AND
1.3 V
1.3 V
PARALLEL ENABLE (PE) INPUTS
t h (H) = 0
AC WAVEFORMS (continued)
FAST AND LS TTL DATA
Figure 4
Figure 5
CEP
CET
Figure 3
CP
Q
5-6
1.3 V
t s (H)
t s (H)
P 0 P 1 P 2 P 3
Q 0 Q 1 Q 2 Q 3
COUNT
CET
TC
CP
TC
1.3 V
1.3 V
1.3 V
t h (H) = 0
t h (H) = 0
CP
OTHER CONDITIONS: CP = PE = CEP = MR = H
t s (H)
OTHER CONDITIONS: PE = CEP = CET = MR = H
OTHER CONDITIONS: PE = H, MR = H
t s (L)
1.3 V
1.3 V
Figure 7
t PLH
t PLH
OTHER CONDITIONS: PE = L, MR = H
1.3 V
1.3 V
1.3 V
1.3 V
t h (H) = 0
HOLD
1.3 V
1.3 V
t h (L) = 0
1.3 V
1.3 V
t s (L)
1.3 V
t s (L)
1.3 V
1.3 V
1.3 V
t PHL
1.3 V
1.3 V
HOLD
t h (L) = 0
t PHL
1.3 V
1.3 V
1.3 V
1.3 V
t h (L) = 0

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