CS4341_05 CIRRUS [Cirrus Logic], CS4341_05 Datasheet - Page 23

• Manufacturer Part Number: CS4341_05
• Description: 24-Bit, 96 kHz Stereo DAC with Volume Control
• Manufacturer: CIRRUS [Cirrus Logic]

4.9.4
4.9.4a
DS298F5
SD A
S C L
In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock,
CCLK (see Figure 24 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip
select signal and is used to control SPI writes to the control port. When the device detects a high
to low transition on the AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs
and data is clocked in on the rising edge of CCLK.
To write to the device, follow the procedure below while adhering to the control port Switching
Specifications in section 1.
1) Bring CS low.
2) The address byte on the CDIN pin must then be 00100000.
3) Write to the memory address pointer, MAP. This byte points to the register to be written.
4) Write the desired data to the register pointed to by the MAP.
5) If the INCR bit (see section 4.9.2a) is set to 1, repeat the previous step until all the desired
6) If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary
S tart
SPI Mode
SPI Write
registers are written, then bring CS high.
to bring CS high, and repeat the procedure detailed from step 1. If no further writes to other
registers are desired, bring CS high.
001000
AD0
W
CCLK
CS
CDIN
ACK
Figure 24. Control Port Timing, SPI Mode
M AP
1-8
MAP = Memory Address Pointer
ADDRESS
0010000
CHIP
Figure 23. I²C Read
ACK
Repeated START
Aborted W RITE
or
R/W
001000
MAP
AD0
MSB
byte 1
R
DATA
ACK
byte n
LSB
(pointed to by MAP)
Data 1-8
ACK
(pointed to by MAP)
Data 1-8
CS4341
Stop
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