CS4341_05 CIRRUS [Cirrus Logic], CS4341_05 Datasheet - Page 11

• Manufacturer Part Number: CS4341_05
• Description: 24-Bit, 96 kHz Stereo DAC with Volume Control
• Manufacturer: CIRRUS [Cirrus Logic]

SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK
Notes: 6. The Duty Cycle must be 50% +/− 1/2 MCLK Period.
DS298F5
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate
LRCK Duty Cycle
SCLK Period
SCLK rising to LRCK edge
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
SCLK rising to SDATA hold time
7. See section 4.2.1 for derived internal frequencies.
Parameters
MCLK / LRCK = 512, 256 or 128
*
The SCLK pulses shown are internal to the CS4341. N equals MCLK divided by SCLK
MCLK / LRCK = 384 or 192
*INTERNAL SCLK
*INTERNAL SCLK
Double-Speed Mode
Single-Speed Mode
Figure 12. Internal Serial Mode Input Timing
*
The SCLK pulses shown are internal to the CS4341.
Figure 13. Internal Serial Clock Generation
SDATA
SDATA
MCLK
LRCK
LRCK
(Note 7)
Symbol
1
t
t
t
sclkw
t
t
sclkr
sdlrs
Fs
Fs
sdh
sdh
t
t
sclkr
sdlrs
N
2
t
sdh
--------------------- -
(
--------------------- -
(
--------------------- -
(
512
512
384
--------------- -
SCLK
1.024
1
1
1
Min
)Fs
)Fs
)Fs
45
50
1
4
-
t
sclkw
+
+
+
10
15
15
(Note 6)
N
t
------------- -
Typ
sclkw
-
-
-
-
-
-
-
-
2
Max
51.2
100
55
50
-
-
-
-
-
CS4341
Units
MHz
kHz
kHz
ns
ns
ns
%
%
s
s
11