CS42428 CIRRUS [Cirrus Logic], CS42428 Datasheet - Page 63

• Manufacturer Part Number: CS42428
• Description: 114 dB, 192kHz 8-Ch CODEC WITH PLL
• Manufacturer: CIRRUS [Cirrus Logic]

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
Inputs: Logic 0 = DGND, Logic 1 = VLC, C
Notes: 19. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(For CQ, T
20. Data must be held for sufficient time to bridge the transition time of CCLK.
21. For f
A
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum
allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should
be safe for all possible conditions.
= -10 to +70° C; For DQ, T
sck
<1 MHz.
Parameter
CDOUT
CDIN
CCLK
CS
t css
Figure 59. Control Port Timing - SPI Format
t r2
A
= -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V;
L
= 30 pF)
t dsu
t scl
t f2
(Note 19)
(Note 20)
(Note 21)
(Note 21)
t sch
t dh
Symbol
t pd
t
f
t
t
t
t
t
t
csh
sch
dsu
t
sck
css
t
t
t
scl
dh
pd
r1
f1
r2
f2
Min
1.0
20
66
66
40
15
0
-
-
-
-
-
t csh
Typ
-
-
-
-
-
-
-
-
-
-
-
-
Max
100
100
6.0
50
25
25
-
-
-
-
-
-
CS42428
Units
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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