k9k4g08u1m Samsung Semiconductor, Inc., k9k4g08u1m Datasheet - Page 8

• Manufacturer Part Number: k9k4g08u1m
• Description: 256m X 8 Bit / 128m X 16 Bit / 512m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

K9K4G08U1M
K9F2G08U0M K9F2G16U0M
Figure 1-1. K9F2G08X0M (X8) Functional Block Diagram
Figure 2-1. K9F2G08X0M (X8) Array Organization
V
V
128K Pages
(=2,048 Blocks)
CC
SS
NOTE : Column Address : Starting Address of the Register.
2nd Cycle
CE
RE
WE
3rd Cycle
1st Cycle
4th Cycle
5th Cycle
Command
A
A
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
12
0
- A
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
- A
11
28
I/O 0
A
A
A
A
A
12
20
28
0
8
CLE
& High Voltage
2K Bytes
Page Register
Control Logic
2K Bytes
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Command
Generator
ALE PRE
Register
I/O 1
A
A
A
A
*L
13
21
1
9
I/O 2
A
A
A
WP
A
*L
10
14
22
2
64 Bytes
64 Bytes
I/O 3
A
A
A
A
*L
11
15
23
3
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
x x x x x x x x x x x x
8
I/O 4
A
A
A
*L
*L
16
24
I/O 0 ~ I/O 7
4
(2048 + 64)Byte x 131072
Global Buffers
Data Register & S/A
I/O Buffers & Latches
I/O 5
2048M + 64M Bit
Cache Register
A
A
A
*L
*L
17
25
NAND Flash
5
8 bit
Y-Gating
ARRAY
1 Block = 64 Pages
(128K + 4k) Byte
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
1 Device = (2K+64)B x 64Pages x 2048 Blocks
I/O 6
A
A
A
*L
*L
18
26
6
= (128K + 4K) Bytes
= 2112 Mbits
I/O 7
A
A
A
*L
*L
FLASH MEMORY
19
27
7
Output
Driver
Column Address
Column Address
Row Address
Row Address
Row Address
Preliminary
V
V
CC
SS
I/0 7
I/0 0