k9k4g08u1m Samsung Semiconductor, Inc., k9k4g08u1m Datasheet - Page 37

• Manufacturer Part Number: k9k4g08u1m
• Description: 256m X 8 Bit / 128m X 16 Bit / 512m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

K9K4G08U1M
K9F2G08U0M K9F2G16U0M
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and XXh, 4th cycle ID, 50h respectively.
The command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.
Figure 14. Read ID Operation
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to table 3 for device status after reset operation. If the device is
already in reset state a new reset command will be accepted by the command register. The R/B pin transitions to low for tRST after
the Reset command is written. Refer to Figure 15 below.
Figure 15. RESET Operation
Table3. Device Status
R/B
I/O
CLE
CE
WE
ALE
RE
I/O
X
Operation Mode
X
PRE status
K9F2G08U0M
K9F2G16U0M
Device
90h
FFh
First page data access is ready
x x x x x x x
x x x x x x x
x x x x x x x
x x x x x x x
x x x x x x x
Address. 1cycle
Device Code*(2nd Cycle)
00h
High
t
CLR
x x x x x x x
x x x x x x x
x x x x x x x
x x x x x x x
x x x x x x x
t
DAh
CAh
WHR
After Power-up
t
AR
t
CEA
t
REA
t
RST
Maker code
37
00h command is latched
ECh
Low
3rd Cycle
Device code
80h
80h
Device
Code*
80h
FLASH MEMORY
Waiting for next command
4th Cycle*
4th Cyc.*
15h
55h
After Reset
Preliminary