v54c316162 ETC-unknow, v54c316162 Datasheet - Page 17
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v54c316162
Manufacturer Part Number
v54c316162
Description
200/183/166/143 Volt, Refresh Ultra High Performance Sdram Banks 512kbit
Manufacturer
ETC-unknow
Datasheet
1.V54C316162.pdf
(21 pages)
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M O S E L V I T E L I C
6.2 Write Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
7. Burst Write with Auto-Precharge
Burst Length = 2, CAS latency = 2, 3)
V54C316162V Rev. 2.9 September 2001
CLK
COMMAND
CAS latency = 2
t
CAS latency = 3
I/O’s
CLK
COMMAND
CAS latency = 3
t
CAS latency = 2
I/O’s
CK2,
CK3,
I/O’s
I/O’s
T0
BANK A
ACTIVE
T0
NOP
WRITE A
T1
T1
DIN A 0
NOP
DIN A 0
READ B
T2
T2
don’t care
don’t care
NOP
Auto-Precharge
T3
T3
WRITE A
don’t care
NOP
DIN A
DIN A
0
0
17
T4
T4
DOUT B 0
DIN A
NOP
DIN A
NOP
t
t
WR
WR
1
1
Input data must be removed from the I/O’s at least one clock
cycle before the Read dataAPpears on the outputs to avoid
data contention.
T5
T5
*
*
Bank can be reactivated after trp
DOUT B 0
DOUT B 1
NOP
NOP
*
Begin Autoprecharge
T6
T6
t
DOUT B 1
DOUT B 2
RP
NOP
NOP
t
RP
T7
T7
DOUT B 2
DOUT B 3
NOP
NOP
V54C316162V
T8
T8
DOUT B 3
NOP
NOP