v54c316162 ETC-unknow, v54c316162 Datasheet - Page 13
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v54c316162
Manufacturer Part Number
v54c316162
Description
200/183/166/143 Volt, Refresh Ultra High Performance Sdram Banks 512kbit
Manufacturer
ETC-unknow
Datasheet
1.V54C316162.pdf
(21 pages)
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CLK
COMMAND
CAS latency = 2
t
CAS latency = 3
t
M O S E L V I T E L I C
1. Bank Activate Command Cycle
(CAS latency = 3)
2. Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
V54C316162V Rev. 2.9 September 2001
CK2,
CK3,
I/O’s
I/O’s
CLK
ADDRESS
COMMAND
: “H” or “L”
T0
READ A
Row Addr.
T0
Activate
Bank A
Bank A
T1
NOP
T1
NOP
t
RCD
T2
DOUT A
NOP
T
0
NOP
T3
DOUT A
DOUT A
NOP
Col. Addr.
Precharge
with Auto
T
Bank A
Write A
1
0
13
t
RC
T4
DOUT A
DOUT A
NOP
. . . . . . . . . .
. . . . . . . . . .
. . . . . . . . . .
2
1
T5
DOUT A
DOUT A
NOP
Row Addr.
T
Activate
Bank B
Bank B
3
2
T6
DOUT A
NOP
t
T
RRD
NOP
3
T7
NOP
V54C316162V
Row Addr.
T
Activate
Bank A
Bank A
T8
NOP