88e3015 Marvell Semiconductor, Inc., 88e3015 Datasheet - Page 59

• Manufacturer Part Number: 88e3015
• Description: Integrated 10/100 Fast Ethernet Transceiver
• Manufacturer: Marvell Semiconductor, Inc.

Table 32:
Copyright © 2006 Marvell
October 26, 2006, Advance
B i ts
15
14
13
12
F i e l d
SWReset
Loopback
SpeedLSB
AnegEn
Register 0
PHY Control Register
M o d e
R/W,
SC
R/W
R/W
R/W
Document Classification: Proprietary Information
H W
R s t
0x0
0x0
0x1
0x1
CONFIDENTIAL
S W
R s t
0x0
Retain
Update
Update
D e s c r i p t io n
PHY Software Reset
Writing a 1 to this bit causes the PHY state machines to
be reset. When the reset operation is done, this bit is
cleared to 0 automatically. The reset occurs immedi-
ately.
0 = Normal operation
1 = PHY reset
Enable Loopback Mode
When loopback mode is activated, the transmitter data
presented on TXD is looped back to RXD internally. The
PHY has to be in forced 10 or 100 Mbps mode. Auto-
Negotiation must be disabled.
0 = Disable loopback
1 = Enable loopback
Speed Selection (LSB)
When a speed change occurs, the PHY drops link and
tries to determine speed when Auto-Negotiation is on.
A write to this register bit has no effect unless any one of
the following also occurs:
Software reset is asserted (bit 15) or
Power down (bit 11) transitions from power down to nor-
mal operation.
0 = 10 Mbps
1 = 100 Mbps
Auto-Negotiation Enable
A write to this register bit has no effect unless any one of
the following also occurs:
Software reset is asserted (bit 15, above), Power down
(bit 11, below), or the PHY transitions from power down
to normal operation.
If the AnegEn bit is set to 0, the speed and duplex bits of
the PHY Control Register (register 0) take effect.
If the AnegEn bit is set to 1, speed and duplex advertise-
ment is found in the Auto-Negotiation Advertisement
Register (Register 4).
0 = Disable Auto-Negotiation Process
1 = Enable Auto-Negotiation Process
Doc. No. MV-S103657-00, Rev. C
Page 59