74HC7266D,653 NXP Semiconductors, 74HC7266D,653 Datasheet - Page 2

IC QUAD 2-IN NOR GATE 14SOIC

74HC7266D,653

Manufacturer Part Number
74HC7266D,653
Description
IC QUAD 2-IN NOR GATE 14SOIC
Manufacturer
NXP Semiconductors
Series
74HCr
Datasheet

Specifications of 74HC7266D,653

Number Of Circuits
4
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Logic Type
XNOR (Exclusive NOR)
Number Of Inputs
2
Current - Output High, Low
5.2mA, 5.2mA
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Product
NOR
Logic Family
HC
High Level Output Current
- 5.2 mA
Low Level Output Current
5.2 mA
Propagation Delay Time
11 ns
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Logical Function
XNOR
Number Of Elements
4
Operating Supply Voltage (typ)
5V
Operating Temp Range
-40C to 125C
Package Type
SO
Number Of Outputs
1
Technology
CMOS
Mounting
Surface Mount
Pin Count
14
Operating Temperature Classification
Automotive
Quiescent Current
2uA
Operating Supply Voltage (max)
6V
Operating Supply Voltage (min)
2V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74HC7266D-T
74HC7266D-T
933772270653
Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC7266 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC7266 provide the EXCLUSIVE-NOR function with active push-pull output.
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
SYMBOL
t
C
C
PHL/
Output capability: standard
I
Quad 2-input EXCLUSIVE-NOR gate
I
PD
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
CC
PD
= input frequency in MHz
L
t
category: SSI
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
2
= 25 C; t
V
PARAMETER
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
f
o
CC
) = sum of outputs
2
f
r
i
= t
+ (C
I
I
f
= GND to V
= GND to V
= 6 ns
L
V
CC
2
CC
CC
f
o
) where:
1.5 V
2
.
CONDITIONS
C
note 1
D
L
= 15 pF; V
in W):
CC
= 5 V
TYPICAL
HC
3.5
17
11
Product specification
74HC7266
UNIT
ns
pF
pF

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