74LVC240ABQ,115 NXP Semiconductors, 74LVC240ABQ,115 Datasheet - Page 2

• Manufacturer Part Number: 74LVC240ABQ,115
• Description: IC INVERTER DUAL 4-INPUT 20QFN
• Manufacturer: NXP Semiconductors
• Series: 74LVCr

Specifications of 74LVC240ABQ,115

• Logic Type: Inverter
• Number Of Inputs: 4
• Number Of Circuits: 2
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 1.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Logic Family: LVC
• Number Of Channels Per Chip: 8
• Polarity: Inverting
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.2 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 24 mA
• Low Level Output Current: 24 mA
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 8 / 8
• Output Type: 3-State
• Propagation Delay Time: 16 ns at 1.2 V, 3.5 ns at 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74LVC240ABQ-G; 74LVC240ABQ-G; 935275101115

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
2003 Dec 02
t
t
t
C
C
PHL
PZH
PHZ
SYMBOL
5 V tolerant inputs/outputs for interfacing with 5 V logic
Supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
High-impedance when V
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 to +85 C and 40 to +125 C.
I
PD
Octal buffer/line driver with 5 V tolerant
inputs/outputs; inverting; 3-state
P
f
f
C
V
N = total load switching outputs;
i
o
/t
/t
/t
(C
D
CC
PD
= input frequency in MHz;
L
PLH
PZL
PLZ
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
propagation delay nAn to nYn
3-state output enable time nOE to nYn
3-state output disable time nOE to nYn
input capacitance
power dissipation capacitance per buffer
2
V
CC
= 25 C; t
f
o
2
) = sum of the outputs.
I
f
= GND to V
i
N + (C
CC
r
= t
PARAMETER
= 0 V
f
2.5 ns.
L
CC
.
V
CC
2
f
o
) where:
2
C
C
C
V
DESCRIPTION
The 74LVC240A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V. These
features allow the use of these devices as translators in a
mixed 3.3 and 5 V environment.
The 74LVC240A is an octal non-inverting buffer/line driver
with 3-state outputs. The 3-state outputs are controlled by
the output enable inputs 1OE and 2OE. A HIGH on nOE
causes the outputs to assume a high-impedance
OFF-state. Schmitt-trigger action at all inputs makes the
circuit highly tolerant for slower input rise and fall times.
The 74LVC240A is functionally identical to the
74LVC244A, which has non-inverting outputs.
CC
L
L
L
outputs enabled
outputs disabled
D
= 50 pF; V
= 50 pF; V
= 50 pF; V
in W).
= 3.3 V; notes 1 and 2
CONDITIONS
CC
CC
CC
= 3.3 V
= 3.3 V
= 3.3 V
3.5
4.3
3.7
5.0
10
3.0
TYPICAL
Product specification
74LVC240A
ns
ns
ns
pF
pF
pF
UNIT