cx74063-26 Skyworks Solutions, Inc., cx74063-26 Datasheet - Page 14

• Manufacturer Part Number: cx74063-26
• Description: Transceiver Multi-band Gprs, Edge Applications With Power Ramping Controller Integrated Crystal Oscillator With Output
• Manufacturer: Skyworks Solutions, Inc.

Data Sheet I CX74063-26
• R2 DC Offset Timing
• R3 IP2 Calibration
• R6 VCXO Control
• R7 VCXO Control
SX1 Control Register. This register is used to program the
fractional-N synthesizer, and set the values of the integral-N
divider and the input-R divider. The polarity of the
Phase/Frequency Detector (PFD) may also be defined by this
register. Refer to Table 13.
SX2 Fractional-N Modulo Register. This register is used to
program the 24-bit modulo of the fractional-N synthesizer. The
data is a 22-bit binary coded decimal word that allows the PLL
to lock to precise frequencies. Refer to Table 14.
RX/TX Control Register. This register is used to control divide
ratios and charge pump currents in the transmitter, and to
control gain in the receiver along with the band select function.
Refer to Table 15.
R0 Auxiliary Control Register. This register is used to bypass
the DC offset correction loops and the baseband filters. It also
enables and disables the two on-chip transmit VCOs and
defines the directionality of the LO port, which allows an
external VCO or LO reference to be used or enables the internal
VCO to be monitored. Refer to Table 16.
R2 DC Offset Timing Register. This register sets the timing of
the tracking of the three DC offset cancellation loops and the
time at which the front end turns on relative to the RXENA
signal (pin 1). It allows the front-end to be enabled using the
internal timer. Refer to Table 17.
R3 IP2 Calibration Register. This register is used to perform
2
calibration coefficients. A total of four words need to be set:
IP2 coefficients for I-high band, I-low band, Q-high band, and
Q-low band. Refer to Table 18.
14
MAY 16, 2003
nd
order Intercept Point (IP2) calibration by manually adjusting
[SX Register 1
(bit 3)]
VCXO_EN (Pin 4)
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PLL
BUF_EN
Baseband
Buffer
Figure 7. VCXO Block Diagram
VCCF (Pin 33)
VCCF (Pin 33)
CAP_B
The IP2 coefficient is eight bits long (including polarity) and is
intended to be a factory calibration. An algorithm using a test
tone needs to be used to determine the coefficient for each
individual part.
R4 PAC Timing Control Register. This register is used to set
timing for the PAC pedestal. See Table 19.
R6 and R7 VCXO Control Registers. These registers are used
to control the tuning range and oscillation frequency of the
VCXO. See Tables 20 and 21, respectively.
Electrical and Mechanical Specifications
The absolute maximum ratings of the CX74063-26 are
provided in Table 3. The recommended operating conditions
are specified in Table 4. Electrical specifications are provided
in Tables 5 through 11. Tables 12 through 21, and Figures 9
through 11 provide the serial interface programming states,
functions, and timing curves. Receiver data is shown in Tables
22 through 33 and illustrated in Figures 12 through 20.
Transmit data is illustrated in Figures 21 through 26.
A typical application circuit using the CX74063-26 is shown in
Figure 27. The 56-pin RFLGA package dimensions are
provided in Figure 28 and the tape and reel dimensions are
shown in Figure 29.
Electrostatic Discharge
The CX74063-26 contains Class 1 devices. The following
Electrostatic Discharge (ESD) precautions are recommended:
• Protective outer garments
• Handle device in ESD safeguarded work area
• Transport device in ESD shielded containers
• Monitor and test all ESD protection equipment
• Treat the CX74063-26 as extremely sensitive to ESD
100 kΩ
CAP_A
XTALTUNE (Pin 39)
XTAL (Pin 34)
XTAL_BUF (Pin 30)
to baseband
C1337
103052A