cx74063-26 Skyworks Solutions, Inc., cx74063-26 Datasheet - Page 13

• Manufacturer Part Number: cx74063-26
• Description: Transceiver Multi-band Gprs, Edge Applications With Power Ramping Controller Integrated Crystal Oscillator With Output
• Manufacturer: Skyworks Solutions, Inc.

The DFC is an adaptive circuit that corrects for any VCO center
frequency errors caused by variations of the integrated VCO
circuit, temperature, supply voltage, aging etc. The VCO can be
centered at any frequency in the range from 1.2 GHz to
1.55 GHz. Once centered, the VCO has a minimum analog
tuning range of 30 MHz.
No calibration or data storage is needed for DFC operation. It is
activated by one of two events:
• When the synthesizer is programmed, the rising edge of the
• When changing the level of the SXENA signal from low to
Crystal Oscillator
A crystal oscillator is designed to provide the reference
frequency for the synthesizer. As shown in Figure 7, the
oscillator uses an external crystal to generate an accurate
oscillation frequency. The reference frequency can be changed
through coarse tuning with an integrated capacitor array or fine
tuning with the integrated varactor diode. The coarse tuning is
done by switching in and out (using a digital word programmed
via the serial interface) the capacitor network (CAP_A and
CAP_B) located at the input of the integrated buffer. The fine
tuning is done by providing a tuning voltage to the integrated
varactor diode. Table 20 describes the control bits.
An output buffer is provided to drive the baseband circuitry
(XTALBUF, pin 30). The VCXO and buffer circuitry are powered
from pin 33 (VCCF). When VCCF is ramped to a voltage greater
than 2.6 V, the output buffer powers on. The oscillator core
powers up when pin 4 (VCXO_EN) is set to logic 1. If pin 4 is
tied permanently to logic 1, the R6 VCXO Control Register is set
to a defined state by a power-on reset. Pin 4 should be held
low if an external reference oscillator is used. The buffer may
be disabled by programming bit 3 in the SX1 Control Register
(see Table 13) to logic 0.
Transmit Section
To minimize the post-PA filtering requirements and any
additional post-PA losses, the transmit path consists of a
vector modulator within a frequency translation loop. The
translation loop consists of the following:
• Phase Frequency Detector (PFD) and charge pump
• Mixer with an operating range of 800 MHz to 2 GHz
• An in-loop modulator
• Two programmable dividers
• Two transmit VCOs
Translational Loop
The translational loop takes baseband analog I/Q signals and
modulates them with the mixed product of transmitter output
and LO signal, as shown in Figure 6. The unmodulated result is
compared with a divided down LO at the PFD and the
difference is used to control the transmit VCO. The on-chip
Low Pass Filter (LPF) following the mixer attenuates the
unwanted sidebands as well as harmonics.
103052A
LE signal starts the DFC cycle and,
high, thereby turning on the synthesizer, the rising edge of
the SXENA signal starts the DFC cycle.
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Transmit VCOs
Two on-chip transmit VCOs are designed to meet GSM850,
EGSM900, DCS1800, and PCS1900 requirements. The
transmit VCOs use the same DFC technique as described in the
Synthesizer section to lock the translational loop. The rising
edge on TXENA initializes the transmit DFC.
Power Amplifier Gain Controller
The device contains an error amplifier/integrator to provide
transmit burst control for an external power amplifier (PA). As
shown in Figure 8, when the device is connected to a PA, an
RF detector, and a coupler, a loop is formed that controls the
transmit power in a multi-band wireless application. The error
amplifier amplifies and integrates the voltage difference
between the RF detector output (PDET) and the power control
input (BBVAPC). The output of the integrator is fed to an
internal gain shaper that drives the gain control input (PAVAPC)
of the external RF PA. The device. provides a bandgap voltage
(PDETVCC) which can be used as the supply voltage for the
external peak detector and can source up to 200 µA.
The PA pre-bias is activated after a programmable delay and
time-referenced from the rising edge of TXENA. The time delay
is set using the serial interface. See Table 19 for details.
Digital Interface
The transceiver and synthesizer are controlled by a single
three-wire serial interface. The transmitter, receiver, and
synthesizer are each enabled through external inputs
according to typical timing requirements as shown in Figures
10 and 11.
Band selection for the CX74063-26 is through the three-wire
serial interface. The PCO signal (pin 3) provides a band
selection control output. DC offset calibration and front-end
activation timing can also be controlled by an on-chip signal
sequencer, precluding the need for separate control signals. All
the logic and the three-wire interface inputs are referenced to
the PCO signal (pin 3).
The RX/TX Control Register is used to program the transceiver
and to preset other test word states by setting bit 22 as a
logic 1. If any test words are to be altered from their preset
states, bit 22 must be sent to the RX/TX Control Register again
as a logic 0. Typically, this is done only on power-up since the
device has a zero-power standby mode that retains
programmed test memory.
There are seven additional registers used to program various
functions of the CX74063-26. The SX1 Control Register is used
to program the fractional-N synthesizer and the SX2
Fractional-N Modulo Register is used to program the modulus.
Three auxiliary registers are used to program the transceiver
besides the RX/TX Control Register, and two 24-bit registers
are used to program the synthesizer:
• SX1 Control
• SX2 Fractional-N Modulo
• RX/TX Control
• R0 Auxiliary Control
Data Sheet I CX74063-26
MAY 16, 2003
13